2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)最新文献

REPAIR: Hard-error recovery via re-execution 修复:通过重新执行恢复硬错误

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315139

Jyothish Soman, Negar Miralaei, A. Mycroft, Timothy M. Jones

引用次数: 2

A fast and scalable fault injection framework to evaluate multi/many-core soft error reliability 一种快速可扩展的多核/多核软错误可靠性评估故障注入框架

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315164

F. Rosa, F. Kastensmidt, R. Reis, Luciano Ost

引用次数: 46

Evaluating the impact of spike and flicker noise in phase change memories 评估脉冲和闪烁噪声对相变存储器的影响

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315126

Salin Junsangsri, F. Lombardi, Jie Han

引用次数: 0

Security analysis of logic encryption against the most effective side-channel attack: DPA 逻辑加密对抗最有效的侧信道攻击的安全性分析:DPA

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315143

Muhammad Yasin, Bodhisatwa Mazumdar, Subidh Ali, O. Sinanoglu

引用次数: 43

Low-overhead fault-tolerance for the preconditioned conjugate gradient solver 预条件共轭梯度求解器的低开销容错性

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315136

A. Schöll, Claus Braun, M. Kochte, H. Wunderlich

{"title":"Low-overhead fault-tolerance for the preconditioned conjugate gradient solver","authors":"A. Schöll, Claus Braun, M. Kochte, H. Wunderlich","doi":"10.1109/DFT.2015.7315136","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315136","url":null,"abstract":"Linear system solvers are an integral part for many different compute-intensive applications and they benefit from the compute power of heterogeneous computer architectures. However, the growing spectrum of reliability threats for such nano-scaled CMOS devices makes the integration of fault tolerance mandatory. The preconditioned conjugate gradient (PCG) method is one widely used solver as it finds solutions typically faster compared to direct methods. Although this iterative approach is able to tolerate certain errors, latest research shows that the PCG solver is still vulnerable to transient effects. Even single errors, for instance, caused by marginal hardware, harsh environments, or particle radiation, can considerably affect execution times, or lead to silent data corruption. In this work, a novel fault-tolerant PCG solver with extremely low runtime overhead is proposed. Since the error detection method does not involve expensive operations, it scales very well with increasing problem sizes. In case of errors, the method selects between three different correction methods according to the identified error. Experimental results show a runtime overhead for error detection ranging only from 0.04% to 1.70%.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129171919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Hot spare components for performance-cost improvement in multi-core SIMT 热备组件，提高多核SIMT的性能成本

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315135

S. H. Mozafari, B. Meyer

引用次数: 6

Quest for a quantum search algorithm for testing stuck-at faults in digital circuits 一种用于数字电路卡滞故障测试的量子搜索算法

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315149

M. Venkatasubramanian, V. Agrawal, James J. Janaher

{"title":"Quest for a quantum search algorithm for testing stuck-at faults in digital circuits","authors":"M. Venkatasubramanian, V. Agrawal, James J. Janaher","doi":"10.1109/DFT.2015.7315149","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315149","url":null,"abstract":"It is colloquially known that searching for test vectors to test the last few hard to detect stuck-at faults is computationally most expensive and mathematically NP-complete. Due to the complex nature of this problem, attempts made to successfully test a digital circuit for all faults in computational linear time start becoming exponential with an increase in circuit size and complexity. Various algorithms have been proposed where new vectors are generated by using previous successful vectors with similar properties. However, this leads to a bottleneck when trying to find hard to detect stuck-at faults which have only one or two unique tests and their properties may not match other previously successful tests. We propose a new unique algorithm that attempts to vastly improve the test search time for these few hard to detect faults by classifying all test vectors in the vector space in three categories: Category I vectors that activate the desired stuck-at fault but may not propagate it to the primary outputs (POs), Category II vectors that propagate the fault site value to the POs, and Category III vectors that neither activate nor propagate the fault. By bounding our search to vectors in categories I and II, and avoiding category III vectors, it is easier to arrive at the solution faster than other algorithmic implementations. The final solution itself lies in the intersection of categories I and II vectors, and it is easier to search for a test vector in a smaller subset of the large vector space. We have demonstrated the proof of concept and detailed working of our algorithm by comparing it with a random test generator.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134285225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Chip-level anti-reverse engineering using transformable interconnects 使用可转换互连的芯片级反逆向工程

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315145

Shuai Chen, Junlin Chen, Domenic Forte, J. Di, M. Tehranipoor, Lei Wang

引用次数: 29

Low-power LDPC decoder design exploiting memory error statistics 低功耗LDPC解码器设计利用内存错误统计

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315157

Junlin Chen, Lei Wang

引用次数: 6

Piecewise-functional broadside tests based on intersections of reachable states 基于可达状态交集的分段泛函宽边测试

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315150

I. Pomeranz

引用次数: 1