2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)最新文献

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Influence of triple-well technology on laser fault injection and laser sensor efficiency 三井技术对激光断层注入和激光传感器效率的影响

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-04-19 DOI: 10.1109/DFT.2015.7315141

N. Borrel, C. Champeix, E. Kussener, W. Rahajandraibe, M. Lisart, A. Sarafianos, J. Dutertre

{"title":"Influence of triple-well technology on laser fault injection and laser sensor efficiency","authors":"N. Borrel, C. Champeix, E. Kussener, W. Rahajandraibe, M. Lisart, A. Sarafianos, J. Dutertre","doi":"10.1109/DFT.2015.7315141","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315141","url":null,"abstract":"This study is driven by the need to understand the influence of a Deep-Nwell implant on the sensitivity of integrated circuits to laser-induced fault injections. CMOS technologies can be either dual-well or triple-well. Triple-well technology has several advantages compared to dual-well technology in terms of electrical performances. Single-event responses have been widely studied in dual-well whereas SEE (single event effects) in triple-well is not well understood. This paper presents a comparative analysis of soft error rate and countermeasures sensors with for these two techniques in 40 nm and 90 nm CMOS technology. First, laser fault injection on registers were investigated, showing that triple-well technology is more vulnerable. Similarly, we studied the efficiency of Bulk Built-In Current Sensors (BBICS) in detecting laser induced fault injection attempts for both techniques. This sensor was found less effective in triple-well. Finally, a new BBICS compliant with body-biasing adjustments is proposed in order to improve its detection efficiency.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128342171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Towards reliability and performance-aware Wireless Network-on-Chip design 面向可靠性和性能敏感的无线片上网络设计

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 1900-01-01 DOI: 10.1109/DFT.2015.7315163

Michael Opoku Agyeman, K. Tong, T. Mak

{"title":"Towards reliability and performance-aware Wireless Network-on-Chip design","authors":"Michael Opoku Agyeman, K. Tong, T. Mak","doi":"10.1109/DFT.2015.7315163","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315163","url":null,"abstract":"Recently Hybrid Wired-Wireless Network-on-Chip (WiNoC) has emerged to solve the poor scalability and performance issues of modern System-on-Chip (SoC) design. However, conventional on-chip wireless interconnect has a high error rates which have drastic effects on the total reliability of the WiNoC. In this paper, we propose an improved wireless interconnect fabric that is able to achieve a similar error rate as traditional wireline channels as an effort to improve the overall reliability of WiNoCs. A novel transducer is designed to launch surface wave signals into a commercially available thin metal conductor coated with a low cost dielectric material to generate wireless signals with high signal strength. Experimental results show that, for a 60GHz center frequency, the proposed communication fabric can achieve an operational bandwidth of about 60GHz. Compared to existing WiNoCs, the proposed communication fabric can improve the reliability of WiNoCs with average gains of 21.4%, 13.8% and 10.7% performance efficiencies in terms of maximum sustainable load, throughput and delay, respectively.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"2 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121016184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

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