2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)最新文献_第2页

Accelerated microarchitectural Fault Injection-based reliability assessment 基于故障注入的微架构可靠性加速评估

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315134

Manolis Kaliorakis, Sotiris Tselonis, Athanasios Chatzidimitriou, D. Gizopoulos

{"title":"Accelerated microarchitectural Fault Injection-based reliability assessment","authors":"Manolis Kaliorakis, Sotiris Tselonis, Athanasios Chatzidimitriou, D. Gizopoulos","doi":"10.1109/DFT.2015.7315134","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315134","url":null,"abstract":"Statistical Fault Injection on microarchitectural simulators can provide early and accurate reliability characterization for array based hardware components. Besides, microarchitectural fault injectors are easily configurable (facilitating many reliability studies) and orders of magnitude faster than RTL fault injectors, rendering them appropriate tools for early reliability estimation using large and realistic benchmarks. However, the throughput of the fault injection campaigns on microarchitectural simulators remains a bottleneck when a batch of campaigns must run for early reliability estimation of a processor (different microarchitectural characteristics, different workloads). This paper presents two different operation modes on top of a baseline framework for statistical fault injection campaigns, trading off between accuracy and speedup of the injection campaigns with a state-of-the-art out-of-order full-system ×86-64 simulator as experimental vehicle. In the first mode, the injection experiments are stopped and classified as masked due to the following conditions: (i) the fault is over-written after the injection and it hasn't been read earlier, (ii) or the fault is injected on an invalid entry. The second mode has the same termination conditions as the first mode, but the injection experiments can also be terminated when an instruction that has read the faulty entry passes through the commit stage of the ×86-64 out-of-order architecture. In the first mode, we observed a speedup up to 2.92× with no loss of accuracy in the vulnerability measurements for all structures. In the second mode an even higher speedup of up to 4.06× has been obtained with small loss in the accuracy of the vulnerability measurements.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129950991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Reliable hash trees for post-quantum stateless cryptographic hash-based signatures 用于后量子无状态加密哈希签名的可靠哈希树

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315144

Mehran Mozaffari Kermani, R. Azarderakhsh

{"title":"Reliable hash trees for post-quantum stateless cryptographic hash-based signatures","authors":"Mehran Mozaffari Kermani, R. Azarderakhsh","doi":"10.1109/DFT.2015.7315144","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315144","url":null,"abstract":"The potential advent of quantum computers in coming years has motivated security researchers to start developing resistant systems capable of thwarting future attacks, i.e., developing post-quantum cryptographic approaches. Hash-based, code-based, lattice-based, multivariate-quadratic-equations, and secret-key cryptography are all potential candidates, the merit of which is that they are believed to resist both classical and quantum computers and applying “Shor's algorithm”-the quantum-computer discrete-logarithm algorithm that breaks classical schemes-to them is infeasible. In this paper, we propose reliable and error detection hash trees for stateless hash-based signatures which are believed to be one of the prominent post-quantum schemes, offering security proofs relative to plausible properties of the hash function. We note that this work on the emerging area of reliable, error detection post-quantum cryptography, can be extended and scaled to other approaches as well. We also note that the proposed approaches make such schemes more reliable against natural faults and help protecting them against malicious faults. We propose, benchmark, and discuss fault diagnosis methods for this post-quantum cryptography variant choosing a case study for hash functions, and present the simulations and implementations results to show the applicability of the presented schemes. The presented architectures can be tailored for different reliability objectives based on the resources available, and would initiate the new research area of reliable, error detection postquantum cryptographic architectures.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131747970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 38

Software-based on-chip thermal sensor calibration for DVFS-enabled many-core systems 基于软件的片上热传感器校准，支持dvfs的多核系统

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315132

Sami Teravainen, M. Haghbayan, A. Rahmani, P. Liljeberg, H. Tenhunen

{"title":"Software-based on-chip thermal sensor calibration for DVFS-enabled many-core systems","authors":"Sami Teravainen, M. Haghbayan, A. Rahmani, P. Liljeberg, H. Tenhunen","doi":"10.1109/DFT.2015.7315132","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315132","url":null,"abstract":"Due to increase in power density and temperature gradient in modern chips, multiple thermal sensors are deployed on the chip area to provide realtime temperature feedback for fine-grained dynamic thermal management (DTM) techniques. Thermal sensor accuracy is extremely prone to intra-die process variation and aging phenomena, and its report gradually drifts from the nominal value. This necessitates efficient calibration techniques to be applied before the sensor values are used. In addition, in modern many-core systems which are often enabled with dynamic voltage and frequency scaling (DVFS), thermal sensors located on cores are sensitive to the core's current voltage-frequency (VF) level, meaning that dedicated calibration is needed for each VF level. In this paper, we propose a general-purpose software-based auto-calibration strategy for thermal sensors without using any hardware infrastructures for DVFS-enabled many-core systems. We adopt a 2-point calibration method for calculating the calibration constants of each thermal sensor at each VF level. We demonstrate the efficiency of the proposed calibration strategy on a many-core platform, Intel's Single-chip Cloud Computer (SCC), covering all voltage and frequency combinations on the platform.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"450 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113982370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation 通过硬件CRC和混淆增强嵌入式SRAM的安全性和容错性

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315147

Senwen Kan, M. Ottavi, Jennifer Dworak

引用次数: 7

On-line detection of intermittent faults in digital-to-analog converters 数模转换器间歇故障的在线检测

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315137

M. Soma

引用次数: 2

Adaptive fault simulation on many-core microprocessor systems 多核微处理器系统的自适应故障仿真

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315153

M. Haghbayan, Sami Teravainen, A. Rahmani, P. Liljeberg, H. Tenhunen

引用次数: 1

Compacting output responses containing unknowns using an embedded processor 使用嵌入式处理器压缩包含未知数的输出响应

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315154

Kamran Saleem, Sreenivaas S. Muthyala, N. Touba

{"title":"Compacting output responses containing unknowns using an embedded processor","authors":"Kamran Saleem, Sreenivaas S. Muthyala, N. Touba","doi":"10.1109/DFT.2015.7315154","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315154","url":null,"abstract":"In system-on-chip (SOC) designs, embedded processors are frequently present as part of the functional design and can be used to help test the chip or system by providing a software-based test. Previous work has looked at compacting output responses in software by performing signature analysis using either arithmetic operations or by implementing a multi-input signature register (MISR) in software. However, these approaches cannot be used when the output response contains unknown (X) values. While it is possible to precisely mask all X's present in the output response in software, a straightforward approach would require a very large amount of mask data to specify which bits to mask. This paper proposes an efficient method for compacting output responses with X's in software using the concept of canceling X's from signatures as proposed in [Touba 07], Whereas the efficiency of the hardware implementation in [Touba 07] is constrained by needing to minimize the hardware overhead, in software these constraints are not present. Thus, a novel and more efficient implementation is proposed here. Moreover, the efficiency is further improved by incorporating a low cost partial X-masking step in software as well. Results indicate that output responses with significant X densities can be very efficiently compacted using the proposed software-based scheme.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121482934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A non-conservative software-based approach for detecting illegal CFEs caused by transient faults 一种基于非保守软件的暂态故障非法CFEs检测方法

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315166

Diego G. Rodrigues, G. Nazarian, Álvaro Freitas Moreira, L. Carro, G. Gaydadjiev

{"title":"A non-conservative software-based approach for detecting illegal CFEs caused by transient faults","authors":"Diego G. Rodrigues, G. Nazarian, Álvaro Freitas Moreira, L. Carro, G. Gaydadjiev","doi":"10.1109/DFT.2015.7315166","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315166","url":null,"abstract":"Software-based methods for the detection of control-flow errors caused by transient fault usually consist in the introduction of protecting instructions both at the beginning and at the end of basic blocks. These methods are conservative in nature, in the sense that they assume that all blocks have the same probability of being the target of control flow errors. Because of that assumption they can lead to a considerable increase both in memory and performance overhead during execution time. In this paper, we propose a static analysis that provide a more refined information about which basic blocks can be the target of control-flow-errors caused by single-bit flips. This information can then be used to guide a program transformation in which only susceptible blocks have to be protected. We implemented the static analysis and program transformation in the context of the LLVM framework and performed an extensive fault injection campaign. Our experiments show that this less conservative approach can potentially lead to gains both in memory usage and in execution time while keeping high fault coverage.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122552528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Fault detection and repair of DSC arrays through memristor sensing DSC阵列的忆阻器故障检测与修复

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-11-09 DOI: 10.1109/DFT.2015.7315127

J. Mathew, Yuamfam Yang, M. Ottavia, T. Browna, A. Zampettia, A. Carloa, A. M. Jabirb, D. Pradhan

{"title":"Fault detection and repair of DSC arrays through memristor sensing","authors":"J. Mathew, Yuamfam Yang, M. Ottavia, T. Browna, A. Zampettia, A. Carloa, A. M. Jabirb, D. Pradhan","doi":"10.1109/DFT.2015.7315127","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315127","url":null,"abstract":"Fault tolerant Photovoltaic array used for green energy systems is emerging as an important area of study because of growing emphasis on reliable design. Among various photovoltaic cells Dye Solar Cell (DSC) is a promising low-cost photovoltaic (PV) technology and high energy-conversion efficiency. Recently it has been shown that it has memristive behavior as well. To efficiently support this claim, in this paper we use experimental data to characterize DSC cell and show that it exhibits memristor state behavior and developed a SPICE model. We use memristive DSC cells as sensing devices. This enables us to identify faulty cells in regular DSC. First, we present the model from the experimental data. A search algorithm is defined to identify the faulty components of the DSC array that fulfill the first requirement of a fault tolerant design. The proposed diagnosis method utilizes recently proposed fault detection solution for efficient testing of PV cells in the presence of faults. We divide the array into segments such that any faults is detectable thereby achieving high diagnosis accuracy. The proposed diagnosis method has been validated through SPICE simulation. Spare cells are to repair the faulty array.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121546034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

SEU sensitivity and modeling using pico-second pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology 使用皮秒脉冲激光刺激40纳米CMOS技术的D触发器的SEU灵敏度和建模

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-10-12 DOI: 10.1109/DFT.2015.7315158

C. Champeix, N. Borrel, J. Dutertre, B. Robisson, M. Lisart, A. Sarafianos

{"title":"SEU sensitivity and modeling using pico-second pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology","authors":"C. Champeix, N. Borrel, J. Dutertre, B. Robisson, M. Lisart, A. Sarafianos","doi":"10.1109/DFT.2015.7315158","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315158","url":null,"abstract":"This paper presents the design of a CMOS 40 nm D Flip-Flop cell and reports the laser fault sensitivity mapping both with experiments and simulation results. Theses studies are driven by the need to propose a simulation methodology based on laser/silicon interactions with a complex integrated circuit. In the security field, it is therefore mandatory to understand the behavior of sensitive devices like D Flip-Flops to laser stimulation. In previous works, Roscian et al., Sarafianos et al., Lacruche et al. or Courbon et al. studied the relations between the layout of cells, its different laser-sensitive areas and their associated fault model using laser pulse duration in the nanosecond range. In this paper, we report similar experiments carried out using a shorter laser pulse duration (30 ps instead of 50 ns). We also propose an upgrade of the simulation model they used to take into account laser pulse durations in the picosecond range on a logic gate composed of a large number of transistors for a recent CMOS technology (40 nm).","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132308066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13