Adaptive fault simulation on many-core microprocessor systems

Abstract

Efficiency of Network-on-Chip based many-core microprocessors to implement parallel fault simulation methods for different circuit sizes is explored in this paper. We show that a naive and straightforward execution of fault simulation programs on such systems does not provide the maximum speedup due to severe bottlenecks in off-chip shared memory access at memory controllers. In order to exploit the available massive parallelism of homogenous many-core microprocessors, a runtime approach capable of adaptively balancing the load during the fault simulation process is proposed. We demonstrate the proposed adaptive fault simulation approach on a many-core platform, Intels Single-chip Cloud Computer showing up to 45X speedup compared to a serial fault simulation approach.