Lithography Asia最新文献

{"title":"Latest developments in photosensitive developable bottom anti-reflective coating (DBARC)","authors":"T. Kudo, S. Chakrapani, A. Dioses, Edward Ng, C. Antonio, Deepa S. Parthasarathy, S. Miyazaki, Yuki Ubayashi, Kazuma Yamamoto, Y. Akiyama, Richard A. Collett, M. Neisser, M. Padmanaban","doi":"10.1117/12.837050","DOIUrl":"https://doi.org/10.1117/12.837050","url":null,"abstract":"Developable bottom anti-reflective coatings (DBARC) are an emerging litho material technology. The biggest advantage of DBARC is that it eliminates the plasma etch step, avoiding damage to plasma sensitive layers during implantation. AZ has pioneered developable BARC based on photosensitive cleave as well as crosslink/decrosslink mechanisms. In this paper, we focus on the crosslink/decrosslink concept. DBARC/resist mismatching was corrected both from process and formulation sides. The optimized DBARC showed comparable lithographic performance as conventional BARCs. This paper provides the chemical concept of the photosensitive developable DBARCs, approaches for DBARC/resist matching and performance of photosensitive DBARCs for 248 nm and 193 nm exposures. Recent 193 nm immersion exposure results are also presented.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123189680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Source mask optimization (SMO) at full chip scale using inverse lithography technology (ILT) based on level set methods","authors":"L. Pang, Peter Hu, Danping Peng, Dongxue Chen, T. Cecil, Lin He, G. Xiao, V. Tolani, Thuc H. Dam, Kiho Baik, B. Gleason","doi":"10.1117/12.843578","DOIUrl":"https://doi.org/10.1117/12.843578","url":null,"abstract":"For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. For years, source optimization and mask pattern correction have been conducted as two separate RET steps. For source optimization, the source was optimized based on fixed mask patterns; in other words, OPC and SRAFs were not considered during source optimization. Recently, some new approaches to Source Mask Optimization (SMO) have been introduced for the lithography development stage. The next important step would be the extension of SMO, and in particular the mask optimization in SMO, into full chip. In this paper, a computational framework based on Level Set Method is presented that enables simultaneous source and mask optimization (using Inverse Lithography Technology, or ILT), and can extend the SMO from single clip, to multiple clips, all the way to full chip. Memory and logic device results at the 32nm node and below are presented which demonstrate the benefits of this level-set-method-based SMO and its extendibility to full chip designs.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126287243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Litho-freeze-litho-etch (LFLE) enabling dual wafer flow coat/develop process and freeze CD tuning bake for >200wph immersion ArF photolithography double patterning","authors":"C. Pieczulewski, C. Rosslee","doi":"10.1117/12.837221","DOIUrl":"https://doi.org/10.1117/12.837221","url":null,"abstract":"The SOKUDO DUO track system incorporates a dual-path wafer flow to reduce the burden on the wafer handling unit and enables high-throughput coat/develop/bake processing in-line with semiconductor photolithography exposure (scanner) equipment. Various photolithography-based double patterning process flows were modeled on the SOKUDO DUO system and it was confirmed to be able to process both Litho-Process-Litho-Etch (LPLE)*2 and negative-tone develop process wafers at greater than 200 wafer-per-hour (wph) capability for each litho-pass through the in-line exposure tool. In addition, it is demonstrated that Biased Hot Plates (BHP) with \"cdTune\" software improves litho pattern #1 and litho pattern #2 within wafer CD uniformity. Based primarily on JSR Micro materials for Litho-Freeze- Litho-Etch (LFLE) the coat, develop and bake process CD uniformity improvement results are demonstrated on the SOKUDO RF3S immersion track in-line with ASML XT:1900Gi system at IMEC, Belgium.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122717542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Litho scenario solutions for FinFET SRAM 22nm node","authors":"Shih-en Tseng, S. Wu, Jacques Wang, Jay Kou, O. Mouraille, Reiner Maria Jungblut, Tsann-Bim Chiou, J. Finders, A. Chen, M. Dusa, S. Hsu","doi":"10.1117/12.837495","DOIUrl":"https://doi.org/10.1117/12.837495","url":null,"abstract":"For the development of the most cost effective lithographic solutions for the 22nm node, the lithographic process and relevant requirements on CDU and overlay need to be identified. In this work, 22nm logic SRAM is selected as use case because FinFET SRAM cells are considered to be a potential successor to conventional planar transistors for 22nm node chips. We focus on the back-end layers of FinFET SRAM, including metal and contact. Litho solutions simulated under ideal scanner conditions with the ASML Brion TachyonTM SMO product are shown. This tool co-optimizes a pixilated freeform source and a continuous transmission gray tone mask based on merit functions of edge placement error. Per scenario, these simulations result in a set of preferred litho solutions with respective source and mask. These solutions have to comply with an imaging metric characterized by MEEF and common PW based on typical fab requirements. In a second step the previously generated solutions are evaluated for CDU analysis using realistic scanner error budget. The purpose is to predict the CDU performance of scanner, process and reticle in order to identify the major contributors for every scenario solution.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"7520 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129217090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High power LPP EUV source system development status","authors":"B. Lin, D. Brandt, N. Farrar","doi":"10.1117/12.839488","DOIUrl":"https://doi.org/10.1117/12.839488","url":null,"abstract":"Extreme ultraviolet (EUV) technology has been recognized as the major lithography technology for 22 nm HP and beyond to fulfill Moore's Law, which predicts that circuit dimensions shrink 70% every 2~3 years in order to achieve cost down and obtain greater functionality per unit area. EUV source power is one of the key factors in determining the cost-effectiveness of EUVL compared to other lithography technologies, like double patterning. Only when EUV power can achieve a certain level, the cost of EUV lithography under high volume manufacturing (HVM) can become much more competitive than that of double patterning techniques. In this paper, the performance of the first production Cymer high power laser produced plasma (LPP) EUV source integrated with a 5 sr multi-layer mirror (MLM) collector and fully integrated debris mitigation will be shown. The latest results on power generation, stable and efficient collection, and clean transmission of EUV light through the intermediate focus will be presented. The lifetime of the MLM collector is a critical parameter in the development of extreme ultraviolet LPP lithography sources. Debris mitigation techniques are used to inhibit reflectivity degradation from deposition of target material, sputtering of the multilayer coating, and implantation of incident particles, which can reduce the efficiency of the MLM collector during exposure. The far field images of MLM collector are recorded by intermediate focus metrology with a CCD camera to determine the reflectivity status of the MLM collector during exposure. The results of these debris mitigation techniques are compared through multiple-hour EUV exposure. Testing shows cleanliness at the source-scanner interface acceptable to the limit of detection.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115808524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A proven methodology for detecting photo-resist residue and for qualifying photo-resist material by measuring fluorescence using SP2 bare wafer inspection and SURFmonitor","authors":"D. Feiler, S. Radovanovic, P. Dighe, Arul Kitnan, G. Simpson, Gad Schwager, Alexander Eynis, D. Enidjer","doi":"10.1117/12.837020","DOIUrl":"https://doi.org/10.1117/12.837020","url":null,"abstract":"During the chip making process, complete removal of photo-resist is very critical. Current metrology & analytical methods do not provide enough sensitivity to detect residual amounts of photo-resist remaining on the wafer. Using the novel method described in this study, the Surfscan SP2 and SURFmonitor solution has successfully demonstrated the sensitivity needed to detect residual photo-resist. This method takes advantage of the fact that residual photo-resist, which is organic in nature, will fluoresce. By scanning wafers after the ash and clean step using the SP2 (UV wavelength) unpatterned defect inspection tool equipped with SURFmonitor, it is possible to generate a full-wafer fluorescence SURFimage. This SURFimage was shown to clearly indicate the regions of the wafer where residual photoresist was present.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125682337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advanced patterning solutions based on double exposure: double patterning and beyond","authors":"Y. Bae, Yi Liu, T. Cardolaccia, Ken Spizuoco, R. Bell, L. Joesten, A. Pikon, M. Reilly, Sheri L. Ablaza, P. Trefonas, G. Barclay","doi":"10.1117/12.840461","DOIUrl":"https://doi.org/10.1117/12.840461","url":null,"abstract":"The CD control of the first lithography (L1) patterns is a important issue in the single-etch double patterning (SEDP) process. In this process, L1 patterns are cured either chemically or thermally and then subjected to the second lithography (L2). A chemical curing process using a surface curing agent (SCA) often results in the CD growth due to the \"positive\" interaction between the first and second resists. A thermal curing process using a thermal cure resist (TCR) often results in the CD loss due to the volumetric shrinkage of the L1 patterns during the L2 process. By combining SCA and TCR concepts, we developed a simple \"hybrid\" curing system which offers precise control of the L1 CD after double patterning. This hybrid curing system involves thermal curing followed by a liquid rinse process using a double patterning primer (DPP). DPP is an aqueous solution formulated with SCA components and enhances \"positive\" interaction between L1 and L2 patterns. While CD loss of 5~6nm is observed without DPP treatment, ~11nm CD growth was observed with TCR after DPP treatment. The L1 CD after double patterning was precisely controllable by post-priming bake process with the rate of -0.3nm/°C in the temperature ranging from 120 ~ 150°C. Taking advantage of the CD growth with DPP treatment, we further developed three different advanced patterning schemes: 1. \"Shrink Process Assisted by Double Exposure\" (SPADE I), 2. \"Space Patterning Assisted by Double Exposure\" (SPADE II), and 3. \"Sidewall Patterning Assisted by Double Exposure\" (SPADE III). Using SPADE I, contact hole CD was reduced by 10~30nm and excellent through pitch performance was observed. SPADE I can also improve LER/LWR when used in the formation of smaller trenches. SPADE II was developed for self-aligned pitch splitting of contact holes and SPADE III was developed for self-aligned pitch splitting of lines. In this paper, the use of DPP in various SPADE technologies is described and its potential in the advanced patterning schemes is discussed.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125939799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hierarchical DPT mask planning for contact layer","authors":"Qiao Li, Pradiptya Ghosh, P. Lacour","doi":"10.1117/12.837214","DOIUrl":"https://doi.org/10.1117/12.837214","url":null,"abstract":"LELE/LFLE based double patterning (DPT) with ArF water-based immersion systems has emerged as a strong candidate to first extend lithography to 32nm and below. Mask planning for DPT consists of conflict visualization when design is not manufacturable with DPT and mask assignment either when it is or despite it is not. Concurrent with the advancements in double patterning process, there has been active research [1] [2] [3] [4] addressing the problem of mask planning. As geometries across the chip can potentially involve in the same conflict, DPT decomposition has been recognized as unbounded [5] [4]. We will show in this paper that the unbounded nature of a potential conflict drawing in geometries from across the chip, however, poses little obstacle to efficient conflict visualization or mask assignment. Hierarchy already present in design offers different levels of abstraction for conflicts spanning across various levels of the hierarchy. And pseudo hierarchy from tiles of fully flattened design are even more amenable in that they are already positioned with respect to the flat view, and tiles overlap only marginally when they do. While there have been ample research literature in the mask assignment problem with respect to geometries within cell or flat view of a design, not much have been published on how hierarchy is addressed or any special handling needed for peculiar complexities arising from the presence of hierarchy [5] [6]. Hierarchy adds a subtle but significant dimension to the mask planning problems. This paper investigates contact layer mask planning for DPT, and presents results on two new problems due to hierarchical processing.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122464327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Relaxation properties of dielectric dipoles of photo resist materials","authors":"H. Sasazaki, A. Kawai","doi":"10.1117/12.841126","DOIUrl":"https://doi.org/10.1117/12.841126","url":null,"abstract":"Relaxation properties of dielectric dipoles such as dielectric frequency dispersion, relaxation time, which should be optimized in structural material designing, are characterized. Relaxation times of dielectric dipoles of photo resist materials are characterized by Cole-Cole plot, which is employed to determine a dielectric relaxation time of dipole moment in polymer structure, based on traditional capacitance method in frequency range of 10mHz to 5MHz. The relaxation time of dry film resist (DFR) can be determined to be 12.1s. The validity of dielectric properties of DFR film as a structural material is discussed.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123779325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Micro bubble removal from micro pattern structure under alternating electric field","authors":"H. Sasazaki, A. Kawai","doi":"10.1117/12.841227","DOIUrl":"https://doi.org/10.1117/12.841227","url":null,"abstract":"Various sizes of concave square patterns are used for micro bubble adhesion and removal investigation in a water/methanol mixture solution. As decreasing the surface energy of the solution, the micro bubble is more likely to remove from the square patterns. However, the micro bubble is less likely to remove as decreasing the square size of patterns. The threshold concentration of water/methanol solution for bubble removal can be determined. Based on the surface energy analysis, the adhesion and removal mechanisms of micro bubble can be explained. By applying alternating electric field to an isolated bubble, electric decomposition of water occurred at the electrode surface. The possibility of removal control of micro bubble is discussed.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131946984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}