Jie Li, J. Hwu, Yongdong Liu, S. Rabello, Zhuan-Zhuan Liu, Jiangtao Hu
{"title":"Scatterometry measurement of asymmetric gratings","authors":"Jie Li, J. Hwu, Yongdong Liu, S. Rabello, Zhuan-Zhuan Liu, Jiangtao Hu","doi":"10.1117/12.839821","DOIUrl":"https://doi.org/10.1117/12.839821","url":null,"abstract":"Scatterometry has been used extensively for the characterization of critical dimensions (CD) and detailed sidewall profiles of periodic structures in microelectronics fabrication processes. So far the majority of applications are for symmetric gratings. In most cases devices are designed to be symmetric although errors could occur during fabrication process and result in undesired asymmetry. The problem with conventional optical scatterometry techniques lies in the lack of capability to distinguish between left and right asymmetries. In this work we investigate the possibility of measuring grating asymmetry using Mueller matrix spectroscopic ellipsometry (MM-SE). A patterned hard disk prepared by nano-imprint technique is used for the study. The relief image on the disk sometimes has asymmetrical sidewall profile, presumably due to the uneven separation of the template from the disk. The undesired tilting resist profile causes difficulties to the downstream processes or even makes them fail. Cross-section SEM reveals that the asymmetrical resist lines are typically tilted towards the outer diameter direction. The simulation and experimental data show that certain Mueller matrix elements are proportional to the direction and amplitude of profile asymmetry, providing a direct indication to the sidewall tilting. The tilting parameter can be extracted using rigorous optical critical dimension (OCD) modeling or calibration method. We demonstrate that this technique has good sensitivity for measuring and distinguishing left and right asymmetry caused by sidewall tilting, and can therefore be used for monitoring processes, such as lithography and etch processing, for which symmetric structures are desired.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127447961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Philip C. W. Ng, K. Tsai, Yen-Min Lee, Ting-Han Pei, Fu-Min Wang, Jia-Han Li, A. Chen
{"title":"A fully model-based methodology for simultaneously correcting EUV mask shadowing and optical proximity effects with improved pattern transfer fidelity and process windows","authors":"Philip C. W. Ng, K. Tsai, Yen-Min Lee, Ting-Han Pei, Fu-Min Wang, Jia-Han Li, A. Chen","doi":"10.1117/12.837077","DOIUrl":"https://doi.org/10.1117/12.837077","url":null,"abstract":"Extreme ultraviolet (EUV) lithography is one of the promising candidates for device manufacturing with features smaller than 22 nm. Unlike traditional optical projection systems, EUV light needs to rely on reflective optics and masks with an oblique incidence for image formation in photoresist. The consequence of using a reflective projection system can result in horizontal-vertical (H-V) bias and pattern shift, which are generally referred as shadowing. Approaches proposed to compensate for shadowing effect include changing mask topography, modifying mask focus, and biasing features along the azimuth angle, which are all rule-based. However, the complicated electromagnetic interaction between closely placed circuit patterns can not only induce additional optical proximity effect but also change the shadowing effect. These detailed phenomena cannot be completely taken into account by the rule-based approaches. A fully model-based approach, which integrates an in-house model-based optical proximity correction (OPC) algorithm with rigorous three-dimensional (3D) EUV mask simulation, is proposed to simultaneously compensate for shadowing and optical proximity effects with better pattern transfer fidelity and process windows. Preliminary results indicate that this fully model-based approach outperforms rule-based ones, in terms of geometric printability under process variations.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127550041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yen-Min Lee, Jia-Han Li, Philip C. W. Ng, Ting-Han Pei, Fu-Min Wang, K. Tsai, A. Chen
{"title":"Using transmission line theory to calculate equivalent refractive index of EUV mask multilayer structures for efficient scattering simulation by finite-difference time-domain method","authors":"Yen-Min Lee, Jia-Han Li, Philip C. W. Ng, Ting-Han Pei, Fu-Min Wang, K. Tsai, A. Chen","doi":"10.1117/12.837150","DOIUrl":"https://doi.org/10.1117/12.837150","url":null,"abstract":"The Finite-Difference Time-Domain (FDTD) method is used to study the scattering effects of extreme ultraviolet (EUV) mask. It requires significant amounts of memory and computation time as the fine grid size is needed for simulation. Theoretically, the accuracy can be increased as the mesh size is decreased in FDTD simulation. However, it is not easy to get the accurate simulation results for the multilayer (ML) structures by FDTD method. The transmission line theory is used to calculate the equivalent refractive index for EUV mask ML to simulate the ML as one layer of bulk artificial material. The reflectivities for EUV light with the normal incidence and small-angle oblique incidence in the bulk artificial material and EUV mask ML are simulated by FDTD method. The Fresnel's equation is used to evaluate the numerical errors for these FDTD simulations, and the results show good agreement between them. Using the equivalent refractive index material for EUV multilayer mask can reduce the computation time and have the accuracy with tolerable numerical errors. The ML structure with periodic surface roughness is also studied by this method, and it shows that only half of computation time is needed to substitute ML to a bulk equivalent refractive index material in FDTD simulations. This proposed method can accelerate the simulations of EUV mask designs.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"7520 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130529303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"In-die actinic metrology on photomasks for low k1 lithography","authors":"D. Beyer, U. Buttgereit, T. Scheruebl, A. Zibold","doi":"10.1117/12.839973","DOIUrl":"https://doi.org/10.1117/12.839973","url":null,"abstract":"New lithography techniques like Double Patterning, Computational Lithography and Source Mask Optimization will be used to drive immersion lithography at 193nm to its limits. The photomask will become more and more a critical optical element in the scanner beam path. Precise image transfer of the circuit features into the resist will be key for the mask manufacture and its qualification. The extremely high MEEF values in low k1 lithography dramatically amplify small process variations on the mask features to the wafer print. Complex mask features using sophisticated OPC and assist features require mask metrology under scanner conditions which measured the optical performance of the mask. Double patterning technology tightens the registration and CDU specification of the patterns at the same time. Especially, overlay becomes more and more critical and must be ensured on every die. In-die registration and CD metrology on arbitrary features at scanner wavelength can measure the mask performance precisely and ensure correct print results and high yield in the wafer fab. Moreover even a complete set of phase shift measurements, CD and registration measurements in the die features can help to ensure that mask manufacture and its qualification provide indeed the largest process window for wafer printing. It is key for higher yield and better performance. In this paper an overview about several actinic in-die metrology techniques will be given. Focus will be on application of in-die CD measurements using the Zeiss WLCD tool as well as in-die registration measurements using the Zeiss Prove tool will be shown and discussed.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130966452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dong-han Lee, Jang-sun Kim, Gil-jin Lee, Sang-ho Lee, Yong-jin Cho, Y. Kang, W. Han
{"title":"In-shot (intra-field) overlay measurement considering overlay mark pattern dependency and illumination source dependency","authors":"Dong-han Lee, Jang-sun Kim, Gil-jin Lee, Sang-ho Lee, Yong-jin Cho, Y. Kang, W. Han","doi":"10.1117/12.839675","DOIUrl":"https://doi.org/10.1117/12.839675","url":null,"abstract":"Recently pattern overlay accuracy becomes more important because of the small pitch patterning. Immersion technology enabled usage of hyper NA beyond 1.0 and this technology provided a lot of possibility to make a very small patterns. But there was no significant technical jump for overlay. Therefore chip makers started to compensate non-linear systematic overlay errors. For example, high order inter-field overlay correction is used to improve overlay performance between the tool to tool matching. Now chip makers are planning to compensate in-shot(intra-field) overlay with higher order compensation than before. Scanner vendors provide intra-field matching options such as i-HOPC(intra-field high order process correction - ASML) and SDM (Super Distortion Matching - Nikon). Those are the methods to match inshot overlay easily. However there are a lot of arguments what the correct way is to measure the in-shot overlay and how we can feedback those measured data to APC system. Especially for the distortion measurement of scanner, we have different data from the mass production trend of distortion. The pattern dependency and another cause of in-shot (intra-field) overlay error will be defined. This will provide a clue to solve difference between the mass production in-shot overlay trend and machine distortion data. The final goal of this study is providing a small hint to design APC system controlling the in-shot(intra-field) overlay with less overlay error.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126912529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Barbu, M. Ivan, P. Giesen, Michael J. Van de Moosdijk, E. Meinders
{"title":"Advances in maskless and mask-based optical lithography on plastic flexible substrates","authors":"I. Barbu, M. Ivan, P. Giesen, Michael J. Van de Moosdijk, E. Meinders","doi":"10.1117/12.837171","DOIUrl":"https://doi.org/10.1117/12.837171","url":null,"abstract":"Organic flexible electronics is an emerging technology with huge potential growth in the future which is likely to open up a complete new series of potential applications such as flexible OLED-based displays, urban commercial signage, and flexible electronic paper. The transistor is the fundamental building block of all these applications. A key challenge in patterning transistors on flexible plastic substrates stems from the in-plane nonlinear deformations as a consequence of foil expansion/shrinkage, moisture uptake, baking etc. during various processing steps. Optical maskless lithography is one of the potential candidates for compensating for these foil distortions by in-situ adjustment prior to exposure of the new layer image with respect to the already patterned layers. Maskless lithography also brings the added value of reducing the cost-of-ownership related to traditional mask-based tools by eliminating the need for expensive masks. For the purpose of this paper, single-layer maskless exposures at 355 nm were performed on gold-coated poly(ethylenenaphthalate) (PEN) flexible substrates temporarily attached to rigid carriers to ensure dimensional stability during processing. Two positive photoresists were employed for this study and the results on plastic foils were benchmarked against maskless as well as mask-based (ASML PAS 5500/100D stepper) exposures on silicon wafers.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126247107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Underwood, David C. Houser, Aaron T. Latzke, R. Perera
{"title":"Challenges in development and construction of stand-alone inspection, metrology, and calibration tools for EUV lithographic applications","authors":"J. Underwood, David C. Houser, Aaron T. Latzke, R. Perera","doi":"10.1117/12.837086","DOIUrl":"https://doi.org/10.1117/12.837086","url":null,"abstract":"Extreme Ultraviolet (EUV) Lithography is currently viewed as the most promising approach for reaching the 22 nm node in the manufacture of silicon devices. One of the principal challenges in the ongoing EUVL research effort is the development of necessary at-wavelength metrology tools. EUV Technology worlds leading manufacturer of EUV metrology tools manufactures custom instrumentation for the utilization and analysis of short wavelength electromagnetic radiation - soft x-rays and extreme ultraviolet (EUV). Our company has pioneered the development of several stand-alone inspection, metrology, and calibration tools for EUV lithographic applications that can be operated in a clean room environment on the floor of a fab. An overview of necessary metrology tools for EUV Lithography will be presented, along with the challenges in developing these tools in order to support the successful implementation of EUV Lithography for the 22nm node. In addition, a detailed description of the EUV metrology tools we have delivered, their long term performance and stability of these tools along with our plans for developing a Reflectometer to achieve the HVM requirements will be discussed.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125218494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"3D integration opportunities, issues, and solutions: a designer's perspective","authors":"D. Kwai, Cheng-Wen Wu","doi":"10.1117/12.845747","DOIUrl":"https://doi.org/10.1117/12.845747","url":null,"abstract":"As the development cost of a typical system-on-chip (SOC) using state-of-the-art technology soars, more and more people turn to three-dimensional (3D) integration for possible alternatives that provide better or equal performance with lower cost. Stacking dies using the through-silicon-via (TSV) technology has been considered one of the most promising solutions to extending the life of Moore's law in semiconductor industry, but of course there are problems to be solved before the infrastructure can be set up to support the industry for manufacturing TSV-based 3D integrated devices. In this paper we will discuss the opportunities, design and manufacturing issues, and possible solutions for 3D integrated devices, from a designer's perspective.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"7520 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131207474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The LER/LWR metrology challenge for advance process control through 3D-AFM and CD-SEM","authors":"P. Faurie, J. Foucher, A. Foucher","doi":"10.1117/12.837311","DOIUrl":"https://doi.org/10.1117/12.837311","url":null,"abstract":"The continuous shrinkage in dimensions of microelectronic devices has reached such level, with typical gate length in advance R&D of less than 20nm combine with the introduction of new architecture (FinFET, Double gate...) and new materials (porous interconnect material, 193 immersion resist, metal gate material, high k materials...), that new process parameters have to be well understood and well monitored to guarantee sufficient production yield in a near future. Among these parameters, there are the critical dimensions (CD) associated to the sidewall angle (SWA) values, the line edge roughness (LER) and the line width roughness (LWR). Thus, a new metrology challenge has appeared recently and consists in measuring \"accurately\" the fabricated patterns on wafers in addition to measure the patterns on a repeatable way. Therefore, a great effort has to be done on existing techniques like CD-SEM, Scatterometry and 3D-AFM in order to develop them following the two previous criteria: Repeatability and Accuracy. In this paper, we will compare the 3D-AFM and CD-SEM techniques as a mean to measure LER and LWR on silicon and 193 resist and point out CD-SEM impact on the material during measurement. Indeed, depending on the material type, the interaction between the electron beam and the material or between the AFM tip and the material can vary a lot and subsequently can generate measurements bias. The first results tend to show that depending on CD-SEM conditions (magnification, number of acquisition frames) the final outputs can vary on a large range and therefore show that accuracy in such measurements are really not obvious to obtain. On the basis of results obtained on various materials that present standard sidewall roughness, we will show the limit of each technique and will propose different ways to improve them in order to fulfil advance roadmap requirements for the development of the next IC generation.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131929610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"FAST-LH: a manufacturing-environmental friendly method of lens heating monitoring","authors":"S. I. Yet, F. Lim","doi":"10.1117/12.836991","DOIUrl":"https://doi.org/10.1117/12.836991","url":null,"abstract":"Lens heating monitoring is crucial for photolithography process control; ineffective lens heating compensation will cause severe focus and image drift on photoresist pattern. Conventional/standard lens heat-test recommended by equipment vendor normally requires long measuring time which is not manufacturing-environmental friendly, and it is designed more to equipment perspective. A fast and accurate method of lens heating monitoring (FAST-LH) is discussed in this paper. Focus drift induced by lens heating is measured using both conventional and FAST-LH; result comparison shows strong correlation of focus drift with the new measuring method. Detailed methodology for the lens heating monitoring is studied; a fine tuned new measuring method is proven to be not only fast but also accurate to monitor lens heating LC compensation rate. Compared to the conventional method, FAST-LH could reflect better the actual focus drift under manufacturing environment. Due to the limitation of transforming the FAST-LH to equipment LH compensation settings, the FASTLH is implemented for periodic monitoring and feedback; whereas the conventional method is used during compensation/corrective action.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130308292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}