Hierarchical DPT mask planning for contact layer

Lithography Asia Pub Date : 2009-12-03 DOI:10.1117/12.837214
Qiao Li, Pradiptya Ghosh, P. Lacour
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引用次数: 2

Abstract

LELE/LFLE based double patterning (DPT) with ArF water-based immersion systems has emerged as a strong candidate to first extend lithography to 32nm and below. Mask planning for DPT consists of conflict visualization when design is not manufacturable with DPT and mask assignment either when it is or despite it is not. Concurrent with the advancements in double patterning process, there has been active research [1] [2] [3] [4] addressing the problem of mask planning. As geometries across the chip can potentially involve in the same conflict, DPT decomposition has been recognized as unbounded [5] [4]. We will show in this paper that the unbounded nature of a potential conflict drawing in geometries from across the chip, however, poses little obstacle to efficient conflict visualization or mask assignment. Hierarchy already present in design offers different levels of abstraction for conflicts spanning across various levels of the hierarchy. And pseudo hierarchy from tiles of fully flattened design are even more amenable in that they are already positioned with respect to the flat view, and tiles overlap only marginally when they do. While there have been ample research literature in the mask assignment problem with respect to geometries within cell or flat view of a design, not much have been published on how hierarchy is addressed or any special handling needed for peculiar complexities arising from the presence of hierarchy [5] [6]. Hierarchy adds a subtle but significant dimension to the mask planning problems. This paper investigates contact layer mask planning for DPT, and presents results on two new problems due to hierarchical processing.
接触层的分层DPT掩码规划
基于LELE/LFLE的双图案(DPT)与ArF水基浸没系统已经成为首次将光刻技术扩展到32nm及以下的有力候选。DPT的掩模规划包括:当设计不能用DPT制造时的冲突可视化;当设计可以或尽管不能用DPT制造时的掩模分配。在双模工艺取得进展的同时,针对掩模规划问题的研究也非常活跃[1][2][3][4]。由于芯片上的几何形状可能涉及相同的冲突,DPT分解被认为是无界的[5][4]。我们将在本文中展示,从整个芯片中绘制几何图形的潜在冲突的无界性质,然而,对有效的冲突可视化或掩码分配几乎没有障碍。设计中已经存在的层次结构为跨越层次结构各个层次的冲突提供了不同层次的抽象。完全平面化设计的瓷砖的伪层次结构甚至更容易接受,因为它们已经相对于平面化视图进行了定位,并且当它们重叠时,瓷砖只是略微重叠。虽然关于设计的单元或平面视图内的几何形状的掩模分配问题已经有大量的研究文献,但关于如何解决层次结构或因层次结构的存在而产生的特殊复杂性所需的任何特殊处理的研究文献并不多[5][6]。层次结构为遮罩规划问题增加了一个微妙但重要的维度。本文对DPT的接触层掩模规划进行了研究,并给出了基于分层处理的两个新问题的结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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