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Keynote speech: Data converters for mobile and autonomous applications 主题演讲:移动和自主应用的数据转换器
International Conference on ASIC Pub Date : 2017-10-01 DOI: 10.1109/ASICON.2017.8252394
F. Maloberti
{"title":"Keynote speech: Data converters for mobile and autonomous applications","authors":"F. Maloberti","doi":"10.1109/ASICON.2017.8252394","DOIUrl":"https://doi.org/10.1109/ASICON.2017.8252394","url":null,"abstract":"There is an increasing interest in mobile or autonomous applications, which are for systems that do not need and do not have the possibility of refueling power. The used power must come from the environment by harvesting what is available and transforming it into electrical form. Those systems move around, i.e. they are they nomadic and often are connected object and we call this category IoT. Since available power is very low its consumption becomes a key design parameter. Moreover, transducers transforming the harvested energy into electricity often give rise to very low voltage. The result is that the analog circuits of nomadic applications must work with sub 1-V supply voltages and power consumption in the tens of hundreds of nW range. Digital circuits are power efficient and for very low power circuits they ensure a better sensitivity to supply noise than analog counterparts. Therefore, for modem nomadic systems moving quickly to digital is an essential strategy. Ensuring ultra-low power atmedium-high resolution (9–12 bit) forrelatively low signal bandwidth (100 kHz–1 MHz) is a typical request. SAR converters and sigma-delta modulators are used. Techniques and recent circuit implementations capable of satisfying diverse ranges of specificationsfor mobile and autonomous systems are presented.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131799267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low voltage SRAM sense amplifier with offset cancelling using digitized multiple body biasing 一种采用数字化多体偏置进行偏置抵消的低压SRAM感测放大器
International Conference on ASIC Pub Date : 2015-11-01 DOI: 10.1109/ASICON.2015.7516887
Bingyan Liu, Yong Hei
{"title":"A low voltage SRAM sense amplifier with offset cancelling using digitized multiple body biasing","authors":"Bingyan Liu, Yong Hei","doi":"10.1109/ASICON.2015.7516887","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7516887","url":null,"abstract":"An offset cancelling technique with digitized multiple body biasing (DMBB) has been proposed. In this scheme, transistors threshold voltage mismatch in latch type sense amplifier (SA) is compensated by adjusting the body bias voltage digitally and repeatedly. Simulated results in 130-nm CMOS technology show that the proposed calibration technique can reduce the standard deviation of offset voltage by over 4X comparing to conventional sense amplifier. In addition, this calibration technique only introduces a little area overhead and some calibration clocks.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125464929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design and implementation of precise measuring method for the access time of embedded memory 嵌入式存储器访问时间精确测量方法的设计与实现
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7517138
Yuqing Hu, Lijun Zhang, Youzhong Li, Qixiao Zhang, Erliang Li, Wei Jiang
{"title":"Design and implementation of precise measuring method for the access time of embedded memory","authors":"Yuqing Hu, Lijun Zhang, Youzhong Li, Qixiao Zhang, Erliang Li, Wei Jiang","doi":"10.1109/ASICON.2015.7517138","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7517138","url":null,"abstract":"With the development of semiconductor process technology and circuit design capabilities, the operating frequency of random access memory has been improved dramatically. How to accurately measure the memory random access time especially to measure the random access time of low density embedded memory has encounter so many challenges. The traditional timing measurement method which connects the external ports directly to the internal ports of memory is not feasible since it is of very low efficiency and very low precision. A new method which applies the built-in test circuit to measure embedded memory access time is presented in this paper. Based on 28nm logic process high speed SRAM test chip design as an example, this paper introduces a new timing measuring method as well as circuit design.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"1997 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128219232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array 100MS/s 9位0.43mW SAR ADC，自定义电容阵列
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7517107
Jingjing Wang, Rongjin Xu, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren
{"title":"100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array","authors":"Jingjing Wang, Rongjin Xu, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren","doi":"10.1109/ASICON.2015.7517107","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7517107","url":null,"abstract":"This paper presents a low power 9-bit 100MS/s successive approximation register analog-to-digital converter (SAR ADC) due to the custom capacitor array. In this capacitor array, a brand-new 3-D 1-fF MOM unit capacitor is used as basic capacitor cell. A beneficial improvement to capacitor array structure makes some difference too. The design is fabricated in TSMC IP9M 65nm LP CMOS technology. At the same sampling rates of 100MS/s, the layout simulation of proposed SAR ADC achieves an ENOB of 8.54bit, an SNDR of 53.15dB, an SFDR of 63.14dB and power consumption of 0.43mW under Nyquist sampling. The FOM of the SAR ADC is low to 8.63fJ/conv.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116309267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS charge pump with dual compensation amplifiers for phase-locked loops synthesizer 锁相环合成器用双补偿放大器CMOS电荷泵
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7517128
Litong Nie, Zhigong Wang, Lu Tang, Junliang Wang, L. Gao
{"title":"A CMOS charge pump with dual compensation amplifiers for phase-locked loops synthesizer","authors":"Litong Nie, Zhigong Wang, Lu Tang, Junliang Wang, L. Gao","doi":"10.1109/ASICON.2015.7517128","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7517128","url":null,"abstract":"A Charge Pump (CP) circuit that minimizes the mismatch between the charging and discharging currents and keeps the currents constant across a wide output voltage range is introduced in this paper. Dual rail-to-rail operational amplifiers are used to enable the CP's charge and discharge currents to be matched well and mitigate the pump-current variation in a wide output range. Besides, a unity-gain amplifier is adopted to eliminate the current sharing effect. The proposed CP circuit is designed and realized in a 0.18-μm CMOS process. The test results show that the current mismatch rate can be less than 1% in the output voltage range of 0.2 V to 1.7 V with the charge pump current of 50 μA and current variation less than 1.2%. The average power consumption of this circuits is about 0.72 mW under a 1.8 V supply voltage.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123686534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 100MS/s 5bit fully digital flash ADC with standard cells 具有标准单元的100MS/s 5bit全数字闪存ADC
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7516936
Xiangyan Xue, Xuerong Zhou, Fan Ye, Junyan Ren
{"title":"A 100MS/s 5bit fully digital flash ADC with standard cells","authors":"Xiangyan Xue, Xuerong Zhou, Fan Ye, Junyan Ren","doi":"10.1109/ASICON.2015.7516936","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7516936","url":null,"abstract":"A 5bit fully digital Flash ADC is presented. It's featured with time delay comparators with embedded differential reference. In this design, differential input analog signals are converted to time delays by a pair of voltage to time converters and the two delay signals are eventually latched to acquire corresponding digital code. No reference from outside is needed. By using standard cells from the digital library, this flash ADC is improved a lot in power, area and design complexity compared to conventional mixed signal ADC. It consumes 587μW and achieves an SFDR of 37.9dB, SNDR of 29.1dB under sampling rate of 100MS/s by post simulation, with a FOM of 240fJ/conversion-step.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122398550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An automated test framework for SRAM-based FPGA 基于sram的FPGA自动化测试框架
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7517028
Xuemin Lv, Moucheng Yang, Xuegong Zhou, Lingli Wang
{"title":"An automated test framework for SRAM-based FPGA","authors":"Xuemin Lv, Moucheng Yang, Xuegong Zhou, Lingli Wang","doi":"10.1109/ASICON.2015.7517028","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7517028","url":null,"abstract":"An automated test framework for SRAM-based FPGA is presented. With the framework, test configurations of different categories can be partially or completely generated, and the tests be running using the generated configurations. Data driven design provides the test framework the flexibility of change the user interface and the command line arguments via software configuration files, without modifying the source code of the framework. Experimental results shows that the test framework handles the complicate test flow efficiently, and release the test engineer from the tedious testing work.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117075586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A radiation hardened low-noise voltage-controlled-oscillator using negative feedback based multipath- current-releasing technology 基于负反馈的多径放流技术的抗辐射低噪声压控振荡器
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2017.8252457
Hengzhou Yuan, Jianjun Chen, Bin Liang, Yang Guo
{"title":"A radiation hardened low-noise voltage-controlled-oscillator using negative feedback based multipath- current-releasing technology","authors":"Hengzhou Yuan, Jianjun Chen, Bin Liang, Yang Guo","doi":"10.1109/ASICON.2017.8252457","DOIUrl":"https://doi.org/10.1109/ASICON.2017.8252457","url":null,"abstract":"A radiation harden low-noise voltage controlled oscillator is demonstrated in this paper. By using negative feedback based multipath-current-releasing technology, the anti-radiation capability of the bias circuit of VCO is largely increased. A compatible current steers are used to reduce the gain of VCO. The cascade structure of inverter is used to suppress the intrinsic noise and power supply noise. By increasing the output resistance of current steers with the cascade structure, the supply noise is suppressed. A modified inverter delay stage is designed to reduce the intrinsic noise of VCO. The simulation results of VCO would achieve 108.6dBc/Hz@1MHz. The peak value of turbulence of bias circuits may reduce to 1/8 compared to the original value at least.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"424 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120897330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Data pre-emphasis based retention reliability enhance scheme for MLC NAND Flash memories 基于数据预强调的MLC NAND闪存存储可靠性提高方案
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7517141
Haozhi Ma, Zhongyi Gao, L. Pan, Jun Xu
{"title":"Data pre-emphasis based retention reliability enhance scheme for MLC NAND Flash memories","authors":"Haozhi Ma, Zhongyi Gao, L. Pan, Jun Xu","doi":"10.1109/ASICON.2015.7517141","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7517141","url":null,"abstract":"In this paper, a data pre-emphasis based retention reliability enhance scheme is proposed to overcome the high retention error rate issue of MLC NAND Flash memories. Retention errors in Nand Flash memories are mainly caused by floating gate electrons leakage. As in the scheme, a data pre-emphasis stage is adopt to induce slightly extra floating gate electron injection in highly stressed blocks. The extra electrons significantly suppress the sensitivity to floating gate electrons leakage and realize retention error rate reduction. In the paper, extra floating gate electron injection is realized by word line program disturbance (WPD). The proposed scheme is applied on 2X-nm MLC NAND Flash, and experiment results indicate 67% retention error rate reduction and 14% device endurance extension.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130670182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The compact Vth model for biaxial strained Si NMOSFET 双轴应变Si NMOSFET的紧凑Vth模型
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7517151
Shujuan Yin
{"title":"The compact Vth model for biaxial strained Si NMOSFET","authors":"Shujuan Yin","doi":"10.1109/ASICON.2015.7517151","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7517151","url":null,"abstract":"With the gradual channel approximation and quasi two dimensional analysis method, a threshold voltage model for biaxial strained Si NMOSFET is developed in this paper. The influences of substrate bias, short channel effect, Drain Induced Barrier Lowering effect, narrow channel effect and so on are completely evaluated and fully implemented into this model. Moreover, the model is validated by comparing the simulation results and experimental data from fabricated strained Si NMOSFET. This threshold voltage model is compact and accurate, which can be applied in strained Si circuit's SPICE simulation. It will provide helpful reference for strained Si VLSI circuit design.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"38 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117022521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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