International Conference on ASIC最新文献

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A simulation analysis of back gate effects for FDSOI devices FDSOI器件后门效应的仿真分析
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7517064
Yudong Li, Bo Tang, Jiang Yan
{"title":"A simulation analysis of back gate effects for FDSOI devices","authors":"Yudong Li, Bo Tang, Jiang Yan","doi":"10.1109/ASICON.2015.7517064","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7517064","url":null,"abstract":"A series of FDSOI devices were simulated using TCAD Sentaurus Process and Sentaurus Device in this paper. Different top silicon thickness (tsi), BOX oxide thickness (tbox) and the back gate voltage (Vbg) were adopted. The impacts on the devices were studied and analyzed. The change of Sub-threshold swing (SS), threshold voltage (Vt) and Ion/Ioff were presented. Long channel and Short channel devices were simulated and studied respectively. Appropriate values of tsi, tbox and Vbg could induce a better performance of the FDSOI devices.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116264773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low-power parallel-to-serial conversion circuit for CMOS image sensors 一种用于CMOS图像传感器的低功耗并行串行转换电路
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7517092
Jicun Zhang, Nan Chen, Chuanming Liu, L. Yao
{"title":"A low-power parallel-to-serial conversion circuit for CMOS image sensors","authors":"Jicun Zhang, Nan Chen, Chuanming Liu, L. Yao","doi":"10.1109/ASICON.2015.7517092","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7517092","url":null,"abstract":"A low-power parallel-to-serial conversion circuit for CMOS image sensors (CIS) aimed for high-data-rate and power-restricted applications, is introduced in this paper. Parallel data are scanned and serialized by the delay-locked loop (DLL)-based pulse generator, wired-AND circuit and a current-mode amplifier. Unlike the conventional parallel-to-serial conversion circuit in CMOS image sensors, the proposed circuit doesn't need a clock tree and therefore consumes much less power. The circuit is designed in a 0.35μm CMOS process. The simulation results show that the power consumption of the proposed parallel-to-serial conversion circuit is reduced significantly compared to the conventional circuits especially in high-data-rate CMOS image sensor applications. The proposed circuit for 12-bit × 256-column CMOS image sensor is capable to operate at the data rate of 600 Mbps consuming 4.07 mW, which is 0.7% and 2.5% of the power consumption of the conventional shift-register scheme and the clock-gating scheme, respectively.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123066532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of novel chopper stabilized rail-to-rail operational amplifier 新型斩波稳定轨对轨运算放大器设计
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7516988
Yong Xu, Fei Zhao, Zheng Sun, Yuanliang Wu
{"title":"Design of novel chopper stabilized rail-to-rail operational amplifier","authors":"Yong Xu, Fei Zhao, Zheng Sun, Yuanliang Wu","doi":"10.1109/ASICON.2015.7516988","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7516988","url":null,"abstract":"A chip design of novel chopper stabilized operational amplifier was presented, chopper-wave modulation and demodulation was used in this architecture, and its 1/f noise was decreased largely. To extend input common mode voltage range, a novel rail-to-rail differential amplifier was adapted in the input stage. The range of input common mode voltage was from zero to power supply, and it only consumed about 22μA current. When input signal frequency was 1 KHz, and the output signal THD was only 0.01%.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122174740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Research on reconfigurable multiplier unit based on GF[(28)]4 field of symmetric cryptography 基于对称密码学GF[(28)]4域的可重构乘法器单元研究
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2011.6157308
Jianbo Xu, Z. Dai, Yang Xuan, Yang Su
{"title":"Research on reconfigurable multiplier unit based on GF[(28)]4 field of symmetric cryptography","authors":"Jianbo Xu, Z. Dai, Yang Xuan, Yang Su","doi":"10.1109/ASICON.2011.6157308","DOIUrl":"https://doi.org/10.1109/ASICON.2011.6157308","url":null,"abstract":"Based on the research of the theories and circuits of (2<sup>n</sup>) GF Galois Field multiplier and X multiplier, this paper presented the reconfigurable architecture for Galois Field multiplier, which use GF(2<sup>8</sup>) as basic field and GF[(2<sup>8</sup>)]<sup>4</sup> as extension field. The architecture could flexibly and efficiently support different Galois Field multipliers, such as GF(2<sup>8</sup>), GF[(2<sup>8</sup>)]<sup>2</sup>, GF[(2<sup>8</sup>)]<sup>3</sup> and GF[(2<sup>8</sup>)]<sup>4</sup>. The design had been realized using Altera's FPGA and synthesized and optimized on Synopsys's Design Compiler. The result proved that the maximum frequency could achieve 260MHz on 0.13µm CMOS technology.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126233501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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