发布求助
文献互助 智能选刊 最新文献

International Conference on ASIC最新文献

筛选
英文 中文
An automatic DC-Offset cancellation method and circuit for RF transceivers 一种用于射频收发器的自动直流偏置消除方法和电路
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7517123
Ken Xu, M. Cai, Xiao-Yong He, Zhijian Chen, Weiguo Zheng
{"title":"An automatic DC-Offset cancellation method and circuit for RF transceivers","authors":"Ken Xu, M. Cai, Xiao-Yong He, Zhijian Chen, Weiguo Zheng","doi":"10.1109/ASICON.2015.7517123","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7517123","url":null,"abstract":"This paper presents a novel low-cost automatic DC-Offset cancellation method and circuit for DAC in RF transmitter. The automatic DC-Offset cancellation block consists of one voltage comparator, one 5-bit R-2R auxiliary DAC and a SAR digital block. The proposed DC-Offset cancellation works during power-on sequence, then stores the value of control word in registers and shuts down the comparator and SAR block to save power after the cancellation operation. Unlike other methods, the proposed method has no influence on the desired signal, and does not disturb the work of transceiver. The proposed block is fabricated in 0.13um CMOS process as one sub-block of a RF transceiver. It occupies only 100um * 200um active area, and consumes only 100uA current under 1.2 V power supply. It is a low-cost solution for cancelling DC-Offset voltage both in receivers and transmitters.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116809758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design of a novel high-accuracy LED driving chip 一种新型高精度LED驱动芯片的设计
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7517097
Guangfa Si, Yongsheng Yin, Honghui Deng
{"title":"Design of a novel high-accuracy LED driving chip","authors":"Guangfa Si, Yongsheng Yin, Honghui Deng","doi":"10.1109/ASICON.2015.7517097","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7517097","url":null,"abstract":"A buck type constant-current driving chip is designed and dedicated to driving small power LED lighting. Different from the traditional peak-current control method, with constant referenced peak value and average value of the inductor current in this chip, a new method is used to stabilize the current of the load cycle by cycle. On the one hand, it improves the system's constant-current accuracy, and on the other hand, it enhances the stability of the system. In addition, the power consumption of the control circuit can be effectively reduced by the detection of the inductor current only in its rising phase. The layout of the whole driving chip is completed with TSMC 0.25um BCD process. Simulation result shows that the whole chip size is 1.16mm 0.79mm, overall power consumption of the chip is 2.6mW, system constant-current accuracy is within 3%. It can meet the requirements of driving a small power LED lighting.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128030942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A high reliability synchronous boost converter with spike suppression circuit 带尖峰抑制电路的高可靠性同步升压变换器
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7517082
Jiangping He, Pengfei Liao, Bo Zhang
{"title":"A high reliability synchronous boost converter with spike suppression circuit","authors":"Jiangping He, Pengfei Liao, Bo Zhang","doi":"10.1109/ASICON.2015.7517082","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7517082","url":null,"abstract":"A high reliability boost converter with spike suppression circuit is proposed in this paper. Compared to the traditional boost converter, a novel control logic circuit is designed to control synchronous transistor, the voltage spike at node SW can be suppressed and the reliability is improved. In addition, the two main power switches are avoided to operate in ON state at the same time, so the efficiency is improved. The converters with/without spike suppression circuit are designed and implemented in a 0.5μm standard CMOS process. The simulations and experimental results show that the spike at node SW is reduced in the proposed converter.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"284 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121331273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 8.1 mW 0.1∼2 GHz inductorless CMOS LNTA for software-defined radio applications 用于软件定义无线电应用的8.1 mW 0.1 ~ 2 GHz无电感CMOS LNTA
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7517118
Benqing Guo, Jun Chen, Yao Wang, Haiyan Jin, G. Wen
{"title":"A 8.1 mW 0.1∼2 GHz inductorless CMOS LNTA for software-defined radio applications","authors":"Benqing Guo, Jun Chen, Yao Wang, Haiyan Jin, G. Wen","doi":"10.1109/ASICON.2015.7517118","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7517118","url":null,"abstract":"A wideband inductorless LNTA is proposed in this paper. The active shunt feedback schematic ensures a wideband input matching while the noise cancellation configuration enables a small NF. The adopted current mirror load operating the LNTA in current mode alleviates the NF deterioration under blocker interference and maintains acceptable linearity as well. Simulations in 0.18-μm CMOS technology show that the proposed LNTA achieves a minimum NF of 2 dB, and a maximum transconductance of 92 mS from 0.1 to 2 GHz. A P1dB of -7.5 dBm and an IIP3 of -0.6 dBm are obtained, respectively. The circuit draws only 4.5 mA from a 1.8 V supply.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123331644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Energy-efficient and area-efficient switching scheme for SAR ADCs 一种高效节能的SAR adc转换方案
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7517102
Dongsheng Liu, W. Lei, Yin Liu, Lun Li
{"title":"Energy-efficient and area-efficient switching scheme for SAR ADCs","authors":"Dongsheng Liu, W. Lei, Yin Liu, Lun Li","doi":"10.1109/ASICON.2015.7517102","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7517102","url":null,"abstract":"This paper presents a novel energy-efficient and area-efficient common-mode based switching scheme for charge recovery successive approximation register analog-to-digital converter (CR-SAR ADC). The scheme obtains low-power switching energy owing to the common-mode based charge recovery switching method and a level-shift technique. Compared with the traditional switching scheme, the average switching energy and capacitors are reduced by about 98.44% and 75% respectively, and a high-linear performance is achieved.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"26 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126060588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PS-BloTAM: Pre-sampling based architecture-level temperature analysis methodology PS-BloTAM:基于预采样的架构级温度分析方法
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7517167
Tian Zou, Zuying Luo
{"title":"PS-BloTAM: Pre-sampling based architecture-level temperature analysis methodology","authors":"Tian Zou, Zuying Luo","doi":"10.1109/ASICON.2015.7517167","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7517167","url":null,"abstract":"Efficient Thermal Analysis (TA) plays a crucial role in temperature-aware floorplanning design and Dynamic Power and Temperature Management (DPTM) for Multi-Processor System-on-Chip(MPSoC). To accelerate temperature-aware floorplanning with fixed die area and unchanged heat dissipation system, this work proposes a novel architecture-level TA method PS-BloTAM. It first uses HotSpot to build the pre-sampling thermal resistance (TR) matrix S with a sampling block array. Then, according to size and position of modules in the given floorplanning solution, PS-BloTAM analytically computes this given floorplan's TR matrix R with S. Finally temperatures of modules in different working modes can be easily estimated with previous R. Adopting traditional idea of design library, PS-BloTAM is able to efficiently compute temperature distributions of numerous floor-plans. Experiments show that comparing with HotSpot, PS-BloTAM achieves 43X speedup with average and maximum errors less than 1.65% and 6.64% respectively.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127642220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparison of decoupling resistors and capacitors for increasing the single event upset resistance of SRAM cells 提高SRAM单元单事件扰动电阻的去耦电阻与电容的比较
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7517078
Z. Zheng, Zhentao Li, Ning Qiao, K. Zhao, Fang Yu, Jiajun Luo
{"title":"Comparison of decoupling resistors and capacitors for increasing the single event upset resistance of SRAM cells","authors":"Z. Zheng, Zhentao Li, Ning Qiao, K. Zhao, Fang Yu, Jiajun Luo","doi":"10.1109/ASICON.2015.7517078","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7517078","url":null,"abstract":"The effects of various values and combinations of decoupling resistors and capacitors on the single event upset (SEU) resistance of static random access memory (SRAM) cells with six transistors have been studied by Spice simulations based on a partially-depleted (PD) silicon-on-insulator (SOI) CMOS technology. It is found that there is an effect enhancement for the combination of the decoupling resistors and capacitors in increasing the SEU linear energy transfer (LET) threshold of the cell, compared with the sum of the SEU LET threshold increments resulting from the corresponding resistors and capacitors, respectively. Also, with the product of the resistance r and capacitance c being constant, a larger r produces a higher SEU LET threshold. In addition, the simulation results show that the LET threshold increases nonlinearly with r, while it does linearly with c.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114573572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A wide range PWM signal frequency converter with the identical duty cycle 具有相同占空比的宽范围PWM信号变频器
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7517125
Jiangping He, Jiang Sun, Bo Zhang
{"title":"A wide range PWM signal frequency converter with the identical duty cycle","authors":"Jiangping He, Jiang Sun, Bo Zhang","doi":"10.1109/ASICON.2015.7517125","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7517125","url":null,"abstract":"A wide frequency range PWM signal frequency converter is presented in this paper. Compared to the traditional frequency converter, an improved approach is designed to decrease the duty cycle error between the input signal and the output signal. By capacitor charge storage method, the duty cycle sampling error at the rising/falling edge of the input PWM signal is reduced significantly. The novel frequency transition method is designed and implemented in a 0.5μm standard CMOS process for a low voltage DC fan motor driver. The simulations and experimental results show that the improved frequency conversion approach is available in many applications.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130361984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Welcome to ASICON 2011 欢迎来到ASICON 2011
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/asicon.2011.6157104
Ting-Ao Tang
{"title":"Welcome to ASICON 2011","authors":"Ting-Ao Tang","doi":"10.1109/asicon.2011.6157104","DOIUrl":"https://doi.org/10.1109/asicon.2011.6157104","url":null,"abstract":"","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133712103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A high PSR SOI current-mode bandgap reference 一个高PSR SOI电流模带隙基准
International Conference on ASIC Pub Date : 1900-01-01 DOI: 10.1109/ASICON.2015.7517098
Junli Sheng, Bingjian Jiang, Zhangwen Tang
{"title":"A high PSR SOI current-mode bandgap reference","authors":"Junli Sheng, Bingjian Jiang, Zhangwen Tang","doi":"10.1109/ASICON.2015.7517098","DOIUrl":"https://doi.org/10.1109/ASICON.2015.7517098","url":null,"abstract":"This paper presents a high PSR current mode bandgap references. The circuits are designed with adopting GSMC 130 nm SOI process. The bandgap's output voltage value is 0.528V and current value is 10μA. It is tapped out that the temperature coefficient of voltage reference is 115 ppm/°C from -40°C to 125°C and current reference is less than 59.4 ppm/°C, power consumption is 173 μW, the PSR is 95.8 dB at 100kHz, and adjusting output resistance can realize other output voltage value with no variation on temperature coefficient.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114160896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信