{"title":"带尖峰抑制电路的高可靠性同步升压变换器","authors":"Jiangping He, Pengfei Liao, Bo Zhang","doi":"10.1109/ASICON.2015.7517082","DOIUrl":null,"url":null,"abstract":"A high reliability boost converter with spike suppression circuit is proposed in this paper. Compared to the traditional boost converter, a novel control logic circuit is designed to control synchronous transistor, the voltage spike at node SW can be suppressed and the reliability is improved. In addition, the two main power switches are avoided to operate in ON state at the same time, so the efficiency is improved. The converters with/without spike suppression circuit are designed and implemented in a 0.5μm standard CMOS process. The simulations and experimental results show that the spike at node SW is reduced in the proposed converter.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"284 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A high reliability synchronous boost converter with spike suppression circuit\",\"authors\":\"Jiangping He, Pengfei Liao, Bo Zhang\",\"doi\":\"10.1109/ASICON.2015.7517082\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high reliability boost converter with spike suppression circuit is proposed in this paper. Compared to the traditional boost converter, a novel control logic circuit is designed to control synchronous transistor, the voltage spike at node SW can be suppressed and the reliability is improved. In addition, the two main power switches are avoided to operate in ON state at the same time, so the efficiency is improved. The converters with/without spike suppression circuit are designed and implemented in a 0.5μm standard CMOS process. The simulations and experimental results show that the spike at node SW is reduced in the proposed converter.\",\"PeriodicalId\":382098,\"journal\":{\"name\":\"International Conference on ASIC\",\"volume\":\"284 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASICON.2015.7517082\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2015.7517082","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A high reliability synchronous boost converter with spike suppression circuit
A high reliability boost converter with spike suppression circuit is proposed in this paper. Compared to the traditional boost converter, a novel control logic circuit is designed to control synchronous transistor, the voltage spike at node SW can be suppressed and the reliability is improved. In addition, the two main power switches are avoided to operate in ON state at the same time, so the efficiency is improved. The converters with/without spike suppression circuit are designed and implemented in a 0.5μm standard CMOS process. The simulations and experimental results show that the spike at node SW is reduced in the proposed converter.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
