Ken Xu, M. Cai, Xiao-Yong He, Zhijian Chen, Weiguo Zheng
{"title":"An automatic DC-Offset cancellation method and circuit for RF transceivers","authors":"Ken Xu, M. Cai, Xiao-Yong He, Zhijian Chen, Weiguo Zheng","doi":"10.1109/ASICON.2015.7517123","DOIUrl":null,"url":null,"abstract":"This paper presents a novel low-cost automatic DC-Offset cancellation method and circuit for DAC in RF transmitter. The automatic DC-Offset cancellation block consists of one voltage comparator, one 5-bit R-2R auxiliary DAC and a SAR digital block. The proposed DC-Offset cancellation works during power-on sequence, then stores the value of control word in registers and shuts down the comparator and SAR block to save power after the cancellation operation. Unlike other methods, the proposed method has no influence on the desired signal, and does not disturb the work of transceiver. The proposed block is fabricated in 0.13um CMOS process as one sub-block of a RF transceiver. It occupies only 100um * 200um active area, and consumes only 100uA current under 1.2 V power supply. It is a low-cost solution for cancelling DC-Offset voltage both in receivers and transmitters.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2015.7517123","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper presents a novel low-cost automatic DC-Offset cancellation method and circuit for DAC in RF transmitter. The automatic DC-Offset cancellation block consists of one voltage comparator, one 5-bit R-2R auxiliary DAC and a SAR digital block. The proposed DC-Offset cancellation works during power-on sequence, then stores the value of control word in registers and shuts down the comparator and SAR block to save power after the cancellation operation. Unlike other methods, the proposed method has no influence on the desired signal, and does not disturb the work of transceiver. The proposed block is fabricated in 0.13um CMOS process as one sub-block of a RF transceiver. It occupies only 100um * 200um active area, and consumes only 100uA current under 1.2 V power supply. It is a low-cost solution for cancelling DC-Offset voltage both in receivers and transmitters.