{"title":"基于对称密码学GF[(28)]4域的可重构乘法器单元研究","authors":"Jianbo Xu, Z. Dai, Yang Xuan, Yang Su","doi":"10.1109/ASICON.2011.6157308","DOIUrl":null,"url":null,"abstract":"Based on the research of the theories and circuits of (2<sup>n</sup>) GF Galois Field multiplier and X multiplier, this paper presented the reconfigurable architecture for Galois Field multiplier, which use GF(2<sup>8</sup>) as basic field and GF[(2<sup>8</sup>)]<sup>4</sup> as extension field. The architecture could flexibly and efficiently support different Galois Field multipliers, such as GF(2<sup>8</sup>), GF[(2<sup>8</sup>)]<sup>2</sup>, GF[(2<sup>8</sup>)]<sup>3</sup> and GF[(2<sup>8</sup>)]<sup>4</sup>. The design had been realized using Altera's FPGA and synthesized and optimized on Synopsys's Design Compiler. The result proved that the maximum frequency could achieve 260MHz on 0.13µm CMOS technology.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"89 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Research on reconfigurable multiplier unit based on GF[(28)]4 field of symmetric cryptography\",\"authors\":\"Jianbo Xu, Z. Dai, Yang Xuan, Yang Su\",\"doi\":\"10.1109/ASICON.2011.6157308\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Based on the research of the theories and circuits of (2<sup>n</sup>) GF Galois Field multiplier and X multiplier, this paper presented the reconfigurable architecture for Galois Field multiplier, which use GF(2<sup>8</sup>) as basic field and GF[(2<sup>8</sup>)]<sup>4</sup> as extension field. The architecture could flexibly and efficiently support different Galois Field multipliers, such as GF(2<sup>8</sup>), GF[(2<sup>8</sup>)]<sup>2</sup>, GF[(2<sup>8</sup>)]<sup>3</sup> and GF[(2<sup>8</sup>)]<sup>4</sup>. The design had been realized using Altera's FPGA and synthesized and optimized on Synopsys's Design Compiler. The result proved that the maximum frequency could achieve 260MHz on 0.13µm CMOS technology.\",\"PeriodicalId\":382098,\"journal\":{\"name\":\"International Conference on ASIC\",\"volume\":\"89 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASICON.2011.6157308\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2011.6157308","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Research on reconfigurable multiplier unit based on GF[(28)]4 field of symmetric cryptography
Based on the research of the theories and circuits of (2n) GF Galois Field multiplier and X multiplier, this paper presented the reconfigurable architecture for Galois Field multiplier, which use GF(28) as basic field and GF[(28)]4 as extension field. The architecture could flexibly and efficiently support different Galois Field multipliers, such as GF(28), GF[(28)]2, GF[(28)]3 and GF[(28)]4. The design had been realized using Altera's FPGA and synthesized and optimized on Synopsys's Design Compiler. The result proved that the maximum frequency could achieve 260MHz on 0.13µm CMOS technology.
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