{"title":"The compact Vth model for biaxial strained Si NMOSFET","authors":"Shujuan Yin","doi":"10.1109/ASICON.2015.7517151","DOIUrl":null,"url":null,"abstract":"With the gradual channel approximation and quasi two dimensional analysis method, a threshold voltage model for biaxial strained Si NMOSFET is developed in this paper. The influences of substrate bias, short channel effect, Drain Induced Barrier Lowering effect, narrow channel effect and so on are completely evaluated and fully implemented into this model. Moreover, the model is validated by comparing the simulation results and experimental data from fabricated strained Si NMOSFET. This threshold voltage model is compact and accurate, which can be applied in strained Si circuit's SPICE simulation. It will provide helpful reference for strained Si VLSI circuit design.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"38 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2015.7517151","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
With the gradual channel approximation and quasi two dimensional analysis method, a threshold voltage model for biaxial strained Si NMOSFET is developed in this paper. The influences of substrate bias, short channel effect, Drain Induced Barrier Lowering effect, narrow channel effect and so on are completely evaluated and fully implemented into this model. Moreover, the model is validated by comparing the simulation results and experimental data from fabricated strained Si NMOSFET. This threshold voltage model is compact and accurate, which can be applied in strained Si circuit's SPICE simulation. It will provide helpful reference for strained Si VLSI circuit design.