{"title":"Data pre-emphasis based retention reliability enhance scheme for MLC NAND Flash memories","authors":"Haozhi Ma, Zhongyi Gao, L. Pan, Jun Xu","doi":"10.1109/ASICON.2015.7517141","DOIUrl":null,"url":null,"abstract":"In this paper, a data pre-emphasis based retention reliability enhance scheme is proposed to overcome the high retention error rate issue of MLC NAND Flash memories. Retention errors in Nand Flash memories are mainly caused by floating gate electrons leakage. As in the scheme, a data pre-emphasis stage is adopt to induce slightly extra floating gate electron injection in highly stressed blocks. The extra electrons significantly suppress the sensitivity to floating gate electrons leakage and realize retention error rate reduction. In the paper, extra floating gate electron injection is realized by word line program disturbance (WPD). The proposed scheme is applied on 2X-nm MLC NAND Flash, and experiment results indicate 67% retention error rate reduction and 14% device endurance extension.","PeriodicalId":382098,"journal":{"name":"International Conference on ASIC","volume":"65 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2015.7517141","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, a data pre-emphasis based retention reliability enhance scheme is proposed to overcome the high retention error rate issue of MLC NAND Flash memories. Retention errors in Nand Flash memories are mainly caused by floating gate electrons leakage. As in the scheme, a data pre-emphasis stage is adopt to induce slightly extra floating gate electron injection in highly stressed blocks. The extra electrons significantly suppress the sensitivity to floating gate electrons leakage and realize retention error rate reduction. In the paper, extra floating gate electron injection is realized by word line program disturbance (WPD). The proposed scheme is applied on 2X-nm MLC NAND Flash, and experiment results indicate 67% retention error rate reduction and 14% device endurance extension.