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2010 International SoC Design Conference最新文献

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Advanced SystemBuilder: A tool set for multiprocessor design space exploration 高级SystemBuilder:用于多处理器设计空间探索的工具集
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682967
S. Shibata, S. Honda, H. Tomiyama, H. Takada
{"title":"Advanced SystemBuilder: A tool set for multiprocessor design space exploration","authors":"S. Shibata, S. Honda, H. Tomiyama, H. Takada","doi":"10.1109/SOCDC.2010.5682967","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682967","url":null,"abstract":"This paper presents our integrated system-level design tool set, named Advanced SystemBuilder. Advanced SystemBuilder supports overall methodology for system design and design space exploration, and provides programming model of systems, automatic synthesis capabilities for FPGA-based prototyping, cosimulation and execution profiling. A case study of MPEG4 decoder design shows the effectiveness of the design space exploration methodology with Advanced SystemBuilder.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127558607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Peak power reduction methodology for multi-core systems 多核系统的峰值功率降低方法
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682930
Bongki Lee, Jaehwan Kim, Yeuncheul Jeung, J. Chong
{"title":"Peak power reduction methodology for multi-core systems","authors":"Bongki Lee, Jaehwan Kim, Yeuncheul Jeung, J. Chong","doi":"10.1109/SOCDC.2010.5682930","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682930","url":null,"abstract":"In this paper, we propose the task scheduling for preventing the occurrence of peak power in the multi-core systems considering data dependence. In the mobile system, the peak power reduces the battery lifetime and makes the system unstable. Among the power consumption of system, the proportion of power consumption of core is very large. If cores execute multiple tasks simultaneously, this gives rise to the peak power. Therefore, algorithm to minimize the occurrence of peak power is needed. When multiple tasks are allocated to the multi-core systems, data dependence relations of all tasks should be considered to avoid data interferences. The proposed algorithm to reduce the peak power schedules the tasks with the data dependence information after data dependence analysis. The proposed algorithm is composed of task partitioning step, data dependence analysis step and priority scheduling step. The simulation results show that the proposed algorithm reduce the occurrence of peak power by up to around 11% compared to the existing algorithms.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129009617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A 7b 1GS/s 60mW folding ADC in 65nm CMOS 7b 1GS/s 60mW折叠ADC, 65nm CMOS
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682901
Jung-hyen Lee, B. Michael, Hojin Park, Byeong-ha Park
{"title":"A 7b 1GS/s 60mW folding ADC in 65nm CMOS","authors":"Jung-hyen Lee, B. Michael, Hojin Park, Byeong-ha Park","doi":"10.1109/SOCDC.2010.5682901","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682901","url":null,"abstract":"A 7b 1GS/s CMOS folding ADC is presented. It utilizes improved track-and-hold circuit using simple clock generator and bootstrapped sampling switch, sequential amplifier settling method in amplifier chain. It also uses low-power thermometer-to-binary encoder realized with transmission gate multiplexer and intermediate track-and-hold circuit for high-speed mediumresolution A/D conversion. The proposed ADC achieves about 6.5 effective bits for 250MHz input at 1GS/s. It consumes 60mW from 1.2V single supply. It is fabricated with 65nm LP CMOS process occupying 0.2mm2 active area.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130366600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Pulsed-latch circuits to push the envelope of ASIC design 脉冲锁存电路推动ASIC设计的发展
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682949
Seungwhun Paik, Youngsoo Shin
{"title":"Pulsed-latch circuits to push the envelope of ASIC design","authors":"Seungwhun Paik, Youngsoo Shin","doi":"10.1109/SOCDC.2010.5682949","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682949","url":null,"abstract":"The use of the slow and power-consuming flip-flops is one of the factors that cause a large gap between custom and ASIC designs. A pulsed-latch, which is a latch driven by a brief pulse clock, inherits the advantage of latch while allowing us to use a simple timing model similar to that of flip-flop. As a result, it offers the opportunity of higher performance and lower power consumption within the conventional ASIC design environment. We address challenges and problems specific to pulsed-latch ASIC, and review potential solutions. Some quantitative results are provided to assess the effectiveness of pulsed-latch circuits.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116659366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Performance maximization of 3D-stacked cache memory on DVFS-enabled processor 在启用dvfs的处理器上实现3d堆叠高速缓存的性能最大化
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682975
K. Kang, Jongpil Jung, C. Kyung
{"title":"Performance maximization of 3D-stacked cache memory on DVFS-enabled processor","authors":"K. Kang, Jongpil Jung, C. Kyung","doi":"10.1109/SOCDC.2010.5682975","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682975","url":null,"abstract":"3D integration increases chip integration density, reduces wire length, wire delay and power consumption on wires. However, increased power density causes increase of temperature, which results in the increase of leakage power consumption and performance degradation. In this paper, we propose a solution to compromise these issues on stacking cache memory on a processor core. Experimental results have shown that the proposed method yields, on the average, 16% performance improvement in terms of instructions per second compared to conventional method. The proposed method also reduces energy consumption by 20% on average, in terms of energy per instruction.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132862804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Buffer optimal static scheduling with a throughput constraint for synchronous dataflow applications on multiprocessors 带吞吐量约束的多处理器同步数据流应用程序的缓冲区最优静态调度
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682911
Tae-ho Shin, Hyunok Oh, S. Ha
{"title":"Buffer optimal static scheduling with a throughput constraint for synchronous dataflow applications on multiprocessors","authors":"Tae-ho Shin, Hyunok Oh, S. Ha","doi":"10.1109/SOCDC.2010.5682911","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682911","url":null,"abstract":"This paper determines a static scheduling and the minimal size of arc buffers for a given synchronous dataflow (SDF) graph, satisfying a throughput constraint. Unlike the previous work, we assume that the target architecture and the mapping information are given. In addition we consider the unfolding of the SDF graph to improve the throughput. To solve this problem, we adopt answer set programming (ASP) with constraint programming (CP) technique which always finds optimal solutions. The proposed ASP+CP formulation is compact enough to list the scheduling rules in 27 lines and could be applied to a small-but-practical size of coarse-grain SDF graphs successfully.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132049214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A synthesizable AXI protocol checker for SoC integration 用于SoC集成的可合成的AXI协议检查器
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682961
Chien-Hung Chen, Jiun-Cheng Ju, Ing-Jer Huang
{"title":"A synthesizable AXI protocol checker for SoC integration","authors":"Chien-Hung Chen, Jiun-Cheng Ju, Ing-Jer Huang","doi":"10.1109/SOCDC.2010.5682961","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682961","url":null,"abstract":"System-on-a-Chip (SoC) design has become more and more complexly. Because difference functions components or IPs (Intellectual Property) will be integrated within a chip. The challenge of integration is “how to verify on-chip communication properties”. Although traditional simulation-based on-chip bus protocol checking bus signals to obey bus transaction behavior or not, however, they are still lack of a chip-level dynamic verification to assist hardware debugging. We proposed a rule-based synthesizable AMBA AXI protocol checker. The AXI protocol checker contains 44 rules to check on-chip communication properties accuracy. In the verification strategy, we use the Synopsys VIP (Verification IP) to verify AXI protocol checker. In the experimental results, the chip cost of AXI protocol checker is 70.7K gate counts and critical path is 4.13 ns (about 242 MHz) under TSMC 0.18um CMOS 1P6M Technology.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134537376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Coarse-grained reconfigurable image stream processor architecture for high-definition cameras and camcorders 用于高清摄像机和摄像机的粗粒度可重构图像流处理器架构
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682963
Teng-Yuan Cheng, Tsung-Huang Chen, C. Jason, Shao-Yi Chien
{"title":"Coarse-grained reconfigurable image stream processor architecture for high-definition cameras and camcorders","authors":"Teng-Yuan Cheng, Tsung-Huang Chen, C. Jason, Shao-Yi Chien","doi":"10.1109/SOCDC.2010.5682963","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682963","url":null,"abstract":"The coarse-grained reconfigurable image stream processor (CRISP) architecture is introduced for the image processing demands of high-definition (HD) cameras and camcorders. With several architectural concepts of the reconfigurable architecture, the CRISP architecture is proposed to meet the performance and flexibility requirements of the HD cameras. A multi-frame processing system with CRISP is implemented to achieve the real-time HD video recording and 11M-pixel image processing capability. Compared with the performance of the high-dynamic-range image fusion algorithm implemented with a general-purpose processor, 106 times speed-up is achieved by the proposed processor with high image quality of 42.5dB in PSNR.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114067959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A transmitter with different output timing to compensate for the crosstalk-induced jitter of coupled microstrip lines 一种具有不同输出时序以补偿耦合微带线串扰引起的抖动的变送器
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682896
Hae-Kang Jung, Soo-Min Lee, J. Sim, Hong-June Park
{"title":"A transmitter with different output timing to compensate for the crosstalk-induced jitter of coupled microstrip lines","authors":"Hae-Kang Jung, Soo-Min Lee, J. Sim, Hong-June Park","doi":"10.1109/SOCDC.2010.5682896","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682896","url":null,"abstract":"By using the data timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). The difference in propagation velocity with the signal modes (odd, static, even) is compensated for by sending data earlier or later at TX according to the signal modes, so that the signals of different modes arrive at receiver (RX) at the same time. This transmitter is implemented by using the delay block with low jitter and a 3:1Mux to select one CLKT of the generated three different sampling CLKD, in advance. The TX is implemented by using a 0.18 μm CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124049963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Alternate scaling strategies for Multi-Gate FETs for high-performance and low-power applications 用于高性能和低功耗应用的多栅极场效应管的备选缩放策略
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682924
B. S. Angada, M. Baghini, K. Dinesh, V. Rao
{"title":"Alternate scaling strategies for Multi-Gate FETs for high-performance and low-power applications","authors":"B. S. Angada, M. Baghini, K. Dinesh, V. Rao","doi":"10.1109/SOCDC.2010.5682924","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682924","url":null,"abstract":"This paper focuses on the alternate strategies to enable scaling of Multi-Gate FETs into sub-22 nm nodes. Scaling is not only limited by device level challenges like increasing parasitic resistances and capacitances, but also circuit level challenges like increasing interconnect parasitics, variability etc. The alternate scaling strategies consider both device level and circuit level challenges to obtain overall benefits with scaling.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117252898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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