Jung-hyen Lee, B. Michael, Hojin Park, Byeong-ha Park
{"title":"7b 1GS/s 60mW折叠ADC, 65nm CMOS","authors":"Jung-hyen Lee, B. Michael, Hojin Park, Byeong-ha Park","doi":"10.1109/SOCDC.2010.5682901","DOIUrl":null,"url":null,"abstract":"A 7b 1GS/s CMOS folding ADC is presented. It utilizes improved track-and-hold circuit using simple clock generator and bootstrapped sampling switch, sequential amplifier settling method in amplifier chain. It also uses low-power thermometer-to-binary encoder realized with transmission gate multiplexer and intermediate track-and-hold circuit for high-speed mediumresolution A/D conversion. The proposed ADC achieves about 6.5 effective bits for 250MHz input at 1GS/s. It consumes 60mW from 1.2V single supply. It is fabricated with 65nm LP CMOS process occupying 0.2mm2 active area.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A 7b 1GS/s 60mW folding ADC in 65nm CMOS\",\"authors\":\"Jung-hyen Lee, B. Michael, Hojin Park, Byeong-ha Park\",\"doi\":\"10.1109/SOCDC.2010.5682901\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 7b 1GS/s CMOS folding ADC is presented. It utilizes improved track-and-hold circuit using simple clock generator and bootstrapped sampling switch, sequential amplifier settling method in amplifier chain. It also uses low-power thermometer-to-binary encoder realized with transmission gate multiplexer and intermediate track-and-hold circuit for high-speed mediumresolution A/D conversion. The proposed ADC achieves about 6.5 effective bits for 250MHz input at 1GS/s. It consumes 60mW from 1.2V single supply. It is fabricated with 65nm LP CMOS process occupying 0.2mm2 active area.\",\"PeriodicalId\":380183,\"journal\":{\"name\":\"2010 International SoC Design Conference\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International SoC Design Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCDC.2010.5682901\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International SoC Design Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCDC.2010.5682901","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 7b 1GS/s CMOS folding ADC is presented. It utilizes improved track-and-hold circuit using simple clock generator and bootstrapped sampling switch, sequential amplifier settling method in amplifier chain. It also uses low-power thermometer-to-binary encoder realized with transmission gate multiplexer and intermediate track-and-hold circuit for high-speed mediumresolution A/D conversion. The proposed ADC achieves about 6.5 effective bits for 250MHz input at 1GS/s. It consumes 60mW from 1.2V single supply. It is fabricated with 65nm LP CMOS process occupying 0.2mm2 active area.
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