Alternate scaling strategies for Multi-Gate FETs for high-performance and low-power applications

Abstract

This paper focuses on the alternate strategies to enable scaling of Multi-Gate FETs into sub-22 nm nodes. Scaling is not only limited by device level challenges like increasing parasitic resistances and capacitances, but also circuit level challenges like increasing interconnect parasitics, variability etc. The alternate scaling strategies consider both device level and circuit level challenges to obtain overall benefits with scaling.