A 7b 1GS/s 60mW folding ADC in 65nm CMOS

Abstract

A 7b 1GS/s CMOS folding ADC is presented. It utilizes improved track-and-hold circuit using simple clock generator and bootstrapped sampling switch, sequential amplifier settling method in amplifier chain. It also uses low-power thermometer-to-binary encoder realized with transmission gate multiplexer and intermediate track-and-hold circuit for high-speed mediumresolution A/D conversion. The proposed ADC achieves about 6.5 effective bits for 250MHz input at 1GS/s. It consumes 60mW from 1.2V single supply. It is fabricated with 65nm LP CMOS process occupying 0.2mm2 active area.