Pulsed-latch circuits to push the envelope of ASIC design

Abstract

The use of the slow and power-consuming flip-flops is one of the factors that cause a large gap between custom and ASIC designs. A pulsed-latch, which is a latch driven by a brief pulse clock, inherits the advantage of latch while allowing us to use a simple timing model similar to that of flip-flop. As a result, it offers the opportunity of higher performance and lower power consumption within the conventional ASIC design environment. We address challenges and problems specific to pulsed-latch ASIC, and review potential solutions. Some quantitative results are provided to assess the effectiveness of pulsed-latch circuits.