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Pico-second time interval amplification 皮秒时间间隔放大
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682938
C. Lin, M. Syrzycki
{"title":"Pico-second time interval amplification","authors":"C. Lin, M. Syrzycki","doi":"10.1109/SOCDC.2010.5682938","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682938","url":null,"abstract":"This paper presents a modified Delay Locked Loop (DLL) based Time Difference Amplifier (TDA) that utilizes a Dynamic-Logic Phase Frequency Detector (PFD). The zero dead-zone characteristic of the Dynamic-Logic PFD allows the DLL to eliminate phase error and maintain a stable gain for single picoseconds input time intervals. The TDA has been designed in 0.13μm CMOS technology. The simulation result demonstrates a linear transfer characteristic for an input time interval range from 0 to 90 ps and a gain shift less than 4.2% under ±10% supply voltage variation and temperature range from −40 D to 80D.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126470507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Design of an H.264 decoder with variable pipeline and smart bus arbiter 具有可变流水线和智能总线仲裁器的H.264解码器的设计
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682877
Chanho Lee, Seohoon Yang
{"title":"Design of an H.264 decoder with variable pipeline and smart bus arbiter","authors":"Chanho Lee, Seohoon Yang","doi":"10.1109/SOCDC.2010.5682877","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682877","url":null,"abstract":"H.264 video coding standard is widely used due to the high compression rate and quality. H.264 decoders usually have pipeline architecture by a macroblock or a 4 × 4 sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and higher data bandwidth. We propose variable pipeline architecture for H.264 decoders for efficient decoding and lower the requirement of the bandwidth for the memory bus. A smart bus arbiter is introduced to adjust the priority adaptively so that the access to a reference memory does not degrade the performance of the decoding pipeline. An H.264 decoder is designed and implemented using the proposed architecture to verify the operation using an FPGA.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126572788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Efficient eye diagram determination of strongly coupled lines for differential signals 有效的眼图确定强耦合线的差分信号
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682931
Dongchul Kim, Hyewon Kim, Y. Eo
{"title":"Efficient eye diagram determination of strongly coupled lines for differential signals","authors":"Dongchul Kim, Hyewon Kim, Y. Eo","doi":"10.1109/SOCDC.2010.5682931","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682931","url":null,"abstract":"A new efficient and accurate eye-diagram determination technique for differential signaling is presented. An efficient eye-diagram for the differential transmission lines is determined by decoupling the coupled lines into effective single lines. Introducing the simplest input bit pattern to determine the worst case inter-symbol interference (ISI), the output response for a single line can be readily determined by using Fast Fourier transform technique (FFT). The proposed technique is compared with SPICE W-model-based simulation that employs pseudorandom bit sequence (PRBS) input signals.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115961688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new scan slice encoding scheme with flexible code for test data compression 一种新的扫描片编码方案，具有灵活的编码，用于测试数据的压缩
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682934
Keun-Soo Lee, Hyuntae Park, HyeonUk Son, Sungho Kang
{"title":"A new scan slice encoding scheme with flexible code for test data compression","authors":"Keun-Soo Lee, Hyuntae Park, HyeonUk Son, Sungho Kang","doi":"10.1109/SOCDC.2010.5682934","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682934","url":null,"abstract":"As the design for testability (DFT) is essential in the semiconductor manufacturing, the scan-based architecture is widely used to decrease the test complexity of a chip. However, the scan-based architecture requires high test cost such as the test data volume and the test time. In order to alleviate the test cost problem of the scan-based architecture, a lot of test data compression schemes using the scan slice encoding have been presented. In this paper, we propose a new scan slice encoding scheme with flexible code for test data compression. The proposed scheme fully utilizes the flexible code as the control code or the data code. The flexible code provides supplementary encoding mode without additional control code. As a result, the test cost is significantly reduced by the various encoding mode with low test equipment pin overhead. The experiment results based on ISCAS'89 benchmark circuits show that the test data volume and the test time is reduced up to 82% compared with the original data.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121765659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Series-biased CMOS power amplifiers operating at high voltage for 24 GHz radar applications 在高压下工作的系列偏置CMOS功率放大器，适用于24 GHz雷达应用
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682895
Jong‐Wook Lee, Jia-fu Lin
{"title":"Series-biased CMOS power amplifiers operating at high voltage for 24 GHz radar applications","authors":"Jong‐Wook Lee, Jia-fu Lin","doi":"10.1109/SOCDC.2010.5682895","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682895","url":null,"abstract":"This paper presents two high power K-band CMOS amplifiers operating at high voltages. The amplifiers employed series-bias technique to increase the operating voltage and achieved a high output power level. The technique also allowed the power amplifiers to operate at a low DC current and thus high efficiency was obtained. The series-bias technique allowed overcoming the low voltage constraint of scaled-down CMOS technology, providing practical solution for realizing high power CMOS amplifier. A two-stage amplifier employing the series-bias technique of four cascode power cells showed a maximum small-signal gain of 25.6 dB, an output power of 20 dBm, and a PAE of 12.5 % at 21 GHz. This is the first CMOS power amplifier delivering 100mW output power above 20 GHz. A three-stage series-bias amplifier having common-source transistor showed a small-signal gain of 17.3 dB, an output power of 17.5 dBm, and a PAE of 8.8% at 23.5 GHz. These amplifiers employing the series-bias technique are shown to have a highly favorable figure-of-merit compared to the results obtained from conventional amplifiers.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132649497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Power gated SRAM circuits with data retention capability and high immunity to noise: A comparison for reliability in low leakage sleep mode 具有数据保留能力和高抗噪声能力的电源门控SRAM电路:低漏睡眠模式下可靠性的比较
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682988
Hailong Jiao, V. Kursun
{"title":"Power gated SRAM circuits with data retention capability and high immunity to noise: A comparison for reliability in low leakage sleep mode","authors":"Hailong Jiao, V. Kursun","doi":"10.1109/SOCDC.2010.5682988","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682988","url":null,"abstract":"A new power gated 6T SRAM circuit is proposed in this paper to suppress leakage power consumption in data retention SLEEP mode. A new write assist circuitry is presented to enhance the write margin of the new power gated memory circuit. Design tradeoffs among data stability, power consumption, and write margin are evaluated with different SRAM circuits. The leakage power consumption is reduced by up to 3.84× and the read static noise margin is increased by up to 4.79× with the new memory power gating technique as compared to a previously published power gated 6T SRAM circuit in a UMC 80nm CMOS technology.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114468459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 0.7-V CMOS operational transconductance amplifier with bulk-driven technique 采用体积驱动技术的0.7 v CMOS操作跨导放大器
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682887
M. Shen, Yi-Shuan Wu, Guan-Hung Ke, Po-Chiun Huang
{"title":"A 0.7-V CMOS operational transconductance amplifier with bulk-driven technique","authors":"M. Shen, Yi-Shuan Wu, Guan-Hung Ke, Po-Chiun Huang","doi":"10.1109/SOCDC.2010.5682887","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682887","url":null,"abstract":"This paper presents a two-stage pseudo-differential amplifier. Rail-to-rail operations are achieved by using bulk terminals as the inputs. The positive feedback technique is used to enhance the transconductance with negative conductance. The bulk terminals of all transistors are carefully biased to lower their threshold voltages (Vth) and maximize signal swing. Using a standard 0.18-μm CMOS technology, measurement results demonstrate that gain-bandwidth product is 0.97MHz. The settling time for a 0.7-Vpp step is 2.1/μS. The input referred noise is 0.14mV at 1MHz. All the circuits dissipate 0.107μW under a single 0.7-V power supply.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125553901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Enhenced redundancy analysis for memories using geometric faults based search tree 基于几何故障的搜索树增强存储器冗余分析
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682932
Wooheon Kang, Hyungjun Cho, Sungho Kang
{"title":"Enhenced redundancy analysis for memories using geometric faults based search tree","authors":"Wooheon Kang, Hyungjun Cho, Sungho Kang","doi":"10.1109/SOCDC.2010.5682932","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682932","url":null,"abstract":"With the growth of memory capacity and density, test cost and yield improvement are becoming more important. To increase yield of memory, redundancy analysis (RA) which analyzes the faults in memory is essential. However, the time for finding solutions to repair memories with faulty cells is very huge because most RA algorithms for automatic test equipment (ATE) are based on a tree structure. To reduce the time of memory test & repair is important to increase the memory yield using ATE. In order to reduce the time of memory test & repair, an RA algorithm with an early termination condition is proposed and it builds a geometric faults based search tree. To build the proposed algorithm, the faults in a memory are classified into geometric faults according to their characteristic. The experimental results show the effectiveness of the proposed algorithm.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121974194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dual loop hardened latch circuit for low power application 用于低功耗应用的双回路硬化锁存电路
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682958
S. Sriram, Haiqing Nan, K. Choi
{"title":"Dual loop hardened latch circuit for low power application","authors":"S. Sriram, Haiqing Nan, K. Choi","doi":"10.1109/SOCDC.2010.5682958","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682958","url":null,"abstract":"As technology is scaling down, circuit reliability issues are major concerns because digital circuits are more susceptible to external noise sources. Soft Error is one such source which changes the voltage of internal nodes of the circuit. Hence it is necessary to design soft error (SE) immune digital circuits. In this paper, we proposed a novel SE immune latch circuit which operates at 0.5V using 32nm technology node. Compared to previous hardened latches up to date, the proposed latch circuit completely immunes to SE on any node of the circuit with 26% total delay reduction.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122426976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
16nm P-type carbon nanotube MOSFET device profile optimization for high-speed 高速16nm p型碳纳米管MOSFET器件外形优化
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682921
Yanan Sun, V. Kursun
{"title":"16nm P-type carbon nanotube MOSFET device profile optimization for high-speed","authors":"Yanan Sun, V. Kursun","doi":"10.1109/SOCDC.2010.5682921","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682921","url":null,"abstract":"Carbon nanotube MOSFET (CN-MOSFET) is a promising future device candidate. The electrical characteristics of 16nm P-type CN-MOSFETs are explored in this paper. The optimum P-type CN-MOSFET device profiles with different number of tubes are identified with a low substrate bias voltage for high-speed operation. Technology development guidelines are provided for achieving high-speed, area efficient, and manufacturable integrated circuits with carbon nanotube transistors.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121503654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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