Dual loop hardened latch circuit for low power application

Abstract

As technology is scaling down, circuit reliability issues are major concerns because digital circuits are more susceptible to external noise sources. Soft Error is one such source which changes the voltage of internal nodes of the circuit. Hence it is necessary to design soft error (SE) immune digital circuits. In this paper, we proposed a novel SE immune latch circuit which operates at 0.5V using 32nm technology node. Compared to previous hardened latches up to date, the proposed latch circuit completely immunes to SE on any node of the circuit with 26% total delay reduction.