Power gated SRAM circuits with data retention capability and high immunity to noise: A comparison for reliability in low leakage sleep mode

A new power gated 6T SRAM circuit is proposed in this paper to suppress leakage power consumption in data retention SLEEP mode. A new write assist circuitry is presented to enhance the write margin of the new power gated memory circuit. Design tradeoffs among data stability, power consumption, and write margin are evaluated with different SRAM circuits. The leakage power consumption is reduced by up to 3.84× and the read static noise margin is increased by up to 4.79× with the new memory power gating technique as compared to a previously published power gated 6T SRAM circuit in a UMC 80nm CMOS technology.