{"title":"高速16nm p型碳纳米管MOSFET器件外形优化","authors":"Yanan Sun, V. Kursun","doi":"10.1109/SOCDC.2010.5682921","DOIUrl":null,"url":null,"abstract":"Carbon nanotube MOSFET (CN-MOSFET) is a promising future device candidate. The electrical characteristics of 16nm P-type CN-MOSFETs are explored in this paper. The optimum P-type CN-MOSFET device profiles with different number of tubes are identified with a low substrate bias voltage for high-speed operation. Technology development guidelines are provided for achieving high-speed, area efficient, and manufacturable integrated circuits with carbon nanotube transistors.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"16nm P-type carbon nanotube MOSFET device profile optimization for high-speed\",\"authors\":\"Yanan Sun, V. Kursun\",\"doi\":\"10.1109/SOCDC.2010.5682921\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Carbon nanotube MOSFET (CN-MOSFET) is a promising future device candidate. The electrical characteristics of 16nm P-type CN-MOSFETs are explored in this paper. The optimum P-type CN-MOSFET device profiles with different number of tubes are identified with a low substrate bias voltage for high-speed operation. Technology development guidelines are provided for achieving high-speed, area efficient, and manufacturable integrated circuits with carbon nanotube transistors.\",\"PeriodicalId\":380183,\"journal\":{\"name\":\"2010 International SoC Design Conference\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International SoC Design Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCDC.2010.5682921\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International SoC Design Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCDC.2010.5682921","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
16nm P-type carbon nanotube MOSFET device profile optimization for high-speed
Carbon nanotube MOSFET (CN-MOSFET) is a promising future device candidate. The electrical characteristics of 16nm P-type CN-MOSFETs are explored in this paper. The optimum P-type CN-MOSFET device profiles with different number of tubes are identified with a low substrate bias voltage for high-speed operation. Technology development guidelines are provided for achieving high-speed, area efficient, and manufacturable integrated circuits with carbon nanotube transistors.
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