Design of an H.264 decoder with variable pipeline and smart bus arbiter

Abstract

H.264 video coding standard is widely used due to the high compression rate and quality. H.264 decoders usually have pipeline architecture by a macroblock or a 4 × 4 sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and higher data bandwidth. We propose variable pipeline architecture for H.264 decoders for efficient decoding and lower the requirement of the bandwidth for the memory bus. A smart bus arbiter is introduced to adjust the priority adaptively so that the access to a reference memory does not degrade the performance of the decoding pipeline. An H.264 decoder is designed and implemented using the proposed architecture to verify the operation using an FPGA.