{"title":"皮秒时间间隔放大","authors":"C. Lin, M. Syrzycki","doi":"10.1109/SOCDC.2010.5682938","DOIUrl":null,"url":null,"abstract":"This paper presents a modified Delay Locked Loop (DLL) based Time Difference Amplifier (TDA) that utilizes a Dynamic-Logic Phase Frequency Detector (PFD). The zero dead-zone characteristic of the Dynamic-Logic PFD allows the DLL to eliminate phase error and maintain a stable gain for single picoseconds input time intervals. The TDA has been designed in 0.13μm CMOS technology. The simulation result demonstrates a linear transfer characteristic for an input time interval range from 0 to 90 ps and a gain shift less than 4.2% under ±10% supply voltage variation and temperature range from −40 D to 80D.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Pico-second time interval amplification\",\"authors\":\"C. Lin, M. Syrzycki\",\"doi\":\"10.1109/SOCDC.2010.5682938\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a modified Delay Locked Loop (DLL) based Time Difference Amplifier (TDA) that utilizes a Dynamic-Logic Phase Frequency Detector (PFD). The zero dead-zone characteristic of the Dynamic-Logic PFD allows the DLL to eliminate phase error and maintain a stable gain for single picoseconds input time intervals. The TDA has been designed in 0.13μm CMOS technology. The simulation result demonstrates a linear transfer characteristic for an input time interval range from 0 to 90 ps and a gain shift less than 4.2% under ±10% supply voltage variation and temperature range from −40 D to 80D.\",\"PeriodicalId\":380183,\"journal\":{\"name\":\"2010 International SoC Design Conference\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International SoC Design Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCDC.2010.5682938\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International SoC Design Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCDC.2010.5682938","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents a modified Delay Locked Loop (DLL) based Time Difference Amplifier (TDA) that utilizes a Dynamic-Logic Phase Frequency Detector (PFD). The zero dead-zone characteristic of the Dynamic-Logic PFD allows the DLL to eliminate phase error and maintain a stable gain for single picoseconds input time intervals. The TDA has been designed in 0.13μm CMOS technology. The simulation result demonstrates a linear transfer characteristic for an input time interval range from 0 to 90 ps and a gain shift less than 4.2% under ±10% supply voltage variation and temperature range from −40 D to 80D.