2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)最新文献

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LADA methodologies to localize embedded memory failure 定位嵌入式内存故障的LADA方法
B. Yeoh, M.H. Thor, L.S. Gan, Y. Chan, S. Goh
{"title":"LADA methodologies to localize embedded memory failure","authors":"B. Yeoh, M.H. Thor, L.S. Gan, Y. Chan, S. Goh","doi":"10.1109/IPFA55383.2022.9915715","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915715","url":null,"abstract":"Dynamic Laser Stimulation (DLS) techniques have met with great success to debug integrated circuit (IC) soft failure. Laser assisted device alteration (LADA) is one of the DLS technique well-established to tackle speed-path failure and analysis of defect-free performance limiting circuits. In this work, we discuss atypical LADA analysis to localize system-on-chip (SOC) memory manufacturing soft and hard defects.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115155799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Semantic-Masked Intensity Augmentation for Deep Learning-based Analysis of FPGA Images 基于深度学习的FPGA图像分析的语义掩码强度增强
Deruo Cheng, Yee-Yang Tee, Jingsi Song, Yiqiong Shi, Tong Lin, B. Gwee
{"title":"Semantic-Masked Intensity Augmentation for Deep Learning-based Analysis of FPGA Images","authors":"Deruo Cheng, Yee-Yang Tee, Jingsi Song, Yiqiong Shi, Tong Lin, B. Gwee","doi":"10.1109/IPFA55383.2022.9915735","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915735","url":null,"abstract":"The emergence of data science and deep learning has enabled the automated recognition of circuit elements from the microscopic images of delayered Integrated Circuit (IC) devices, and has greatly improved the efficiency of overall functional analysis flow for hardware security. However, due to the high complexity of delayering the manufactured IC devices and the imaging imperfections in modern ICs, the acquired microscopic images usually contain unforeseeable variations even for the same types of circuit elements. As a result, the deep learning model which is typically trained with a very limited set of labelled images suffers from inefficacy on generalizing to unseen images, which further causes errors for subsequent analysis. Data augmentation techniques, which virtually introduce data variations and increase the data amount by applying different image transformations, are thus widely used during the training of deep learning models for IC image analysis. In this paper, we propose a Semantic-Masked Intensity Augmentation (SMIA) technique with a deep-learning-based framework to analyze the microscopic images acquired from a delayered Field-Programmable Gate Arrays (FPGA) device. Different from the commonly-used intensity augmentation techniques which apply transformations to the image pixels according to their original intensities, our proposed SMIA considers the semantic context of the image pixels by applying different intensity transformations according to pixel-level semantic masks. With experiments on segmenting metal lines from the metal layer images of a targeted FPGA, our proposed SMIA demonstrates better performance and higher stability than the existing intensity augmentation techniques.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122721037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A scalable & comprehensive resilience concept against optical & physical IC backside attacks 针对光学和物理IC背后攻击的可扩展和全面弹性概念
N. Herfurth, E. Amini, M. Lisker, Jean-Pierre Seifert, C. Boit
{"title":"A scalable & comprehensive resilience concept against optical & physical IC backside attacks","authors":"N. Herfurth, E. Amini, M. Lisker, Jean-Pierre Seifert, C. Boit","doi":"10.1109/IPFA55383.2022.9915714","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915714","url":null,"abstract":"IC security is not ensured until the chip backside is fully protected. This paper presents a comprehensive and VLSI-compatible protection structure to secure integrated circuits (ICs) against all types of physical and optical attacks targeting the IC via the chip backside. The novel method of protecting the IC structure is provided by outsourcing the protection scheme onto a dedicated protection wafer. This protection wafer is then irreversibly bonded to the IC. This process can be performed at wafer level, realising a VLSI-compatible protection scheme. An example integration based on the new approach is described and discussed in detail.The protection wafer consists of a highly doped silicon substrate forming an optical opaque layer. The protection wafer is irreversibly bonded to the IC and electrically contacted by through silicon vias (TSVs). Integrity of the wafer-stack is verified by an electro-optical process. The protection wafer contains several photon-emitting devices. Several p-n junctions on the circuit side of the protected IC sense the optical signals generated by the photon emitting devices on the protection wafer.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"76 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123218337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Photon Emission Microscopy of Amorphous HfO2 ReRAM Cells 非晶态HfO2 ReRAM细胞的光子发射显微镜研究
F. Stellari, L. Ocola, E. Wu, T. Ando, P. Song
{"title":"Photon Emission Microscopy of Amorphous HfO2 ReRAM Cells","authors":"F. Stellari, L. Ocola, E. Wu, T. Ando, P. Song","doi":"10.1109/IPFA55383.2022.9915718","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915718","url":null,"abstract":"In this paper, we study the photon emission from filaments formed in amorphous HfO2 Resistive Random-Access Memory (ReRAM) cells and compare it to previous results from crystalline cells. Both a CCD and an InGaAs camera are used to observe the photon emission in set/reset state using forward/reverse bias voltage. An electric field model and a uniform Poisson spatial distribution model can be used to model the photon emission on both types of cell types.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"17 2-3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132483538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimizing EBAC / EBIRCH analysis in 5 nm technology 优化5nm技术的EBAC / EBIRCH分析
A. Rummel, Greg M. Johnson
{"title":"Optimizing EBAC / EBIRCH analysis in 5 nm technology","authors":"A. Rummel, Greg M. Johnson","doi":"10.1109/IPFA55383.2022.9915709","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915709","url":null,"abstract":"An intentionally overstressed fin defect was created in 5 nm technology. EBIC analysis with 0.5 kV electron beam stimulation enabled early detection of the defect during overstress experiments. EBIRCH analysis, again at 0.5 kV was able to isolate the exact spot of the fail in a multi-fin device. Additional EBIC scans at various kVs were also able to isolate the failing fin, located close to the EBIRCH spot, and provided insights on how to use Monte Carlo scattering models to predict the optimal beam energy to find defects via EBIC. This approach could be applied to fails in 5 nm or systems with delicate structures.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134378139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comprehensive Investigation of the Switching Stability in SiC and GaN Power Devices SiC和GaN功率器件开关稳定性的综合研究
Shun-Wei Tang, Chao-Ta Fan, Ming-Cheng Lin, Tian-Li Wu
{"title":"Comprehensive Investigation of the Switching Stability in SiC and GaN Power Devices","authors":"Shun-Wei Tang, Chao-Ta Fan, Ming-Cheng Lin, Tian-Li Wu","doi":"10.1109/IPFA55383.2022.9915772","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915772","url":null,"abstract":"In this work, to the best of our knowledge, it is the first time to report the high-frequency switching stabilities (up to 300kHz) under a 800V of Vds during hard switching (HSW) and zero voltage switching (ZVS) operations in SiC power devices. The switching dependencies, i.e., temperature, frequency, current, and duty cycle, are evaluated based on the proposed topology, showing the flexible design to effectively investigate the circuit-level switching stability. Furthermore, the high-frequency switching stability in GaN power devices is also evaluated for the comparison, indicating that SiC power device shows a better Rdson stability under ZVS and HSW during the high-frequency switching.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132857464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-Voltage a-IGZO Thin Film Transistor with the Symmetrical Stair Gate-Dielectric Structure 具有对称阶梯栅介电结构的高压a-IGZO薄膜晶体管
Guangan Yang, Ting-Hui Huang, Wangran Wu, Hao Tian, Zuoxu Yu, Siyang Liu, Weifeng Sun
{"title":"High-Voltage a-IGZO Thin Film Transistor with the Symmetrical Stair Gate-Dielectric Structure","authors":"Guangan Yang, Ting-Hui Huang, Wangran Wu, Hao Tian, Zuoxu Yu, Siyang Liu, Weifeng Sun","doi":"10.1109/IPFA55383.2022.9915719","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915719","url":null,"abstract":"We fabricated the a-IGZO transistors with the symmetrical stair gate-dielectric structure. The electrical properties of the studied devices are examined in detail. Both the source and drain breakdown voltage (V<inf>BD, GS</inf> and V<inf>BD, GD</inf>) of over 60 V are obtained with the L<inf>stair</inf> of 3 μm. It is observed that the threshold voltage (V<inf>th</inf>) and subthreshold voltage have a negligible variation with the length of the stair region (L<inf>stair</inf>). The transconductance (g<inf>m</inf>) slightly decreases with the L<inf>stair</inf> because the gate capacitance is smaller in the device with the symmetrical stair structure. The distribution of the on-resistance (R<inf>on</inf>) of the stair region (M<inf>stair</inf>) is demonstrated. The simulation is performed to further understand the operation mechanism of the symmetrical stair structure a-IGZO TFTs.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121563398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enhanced EBAC Detection on Gate Oxide Breakdown Isolation after High Voltage Electron Beam Irradiation 高压电子束辐照栅极氧化物击穿隔离的增强EBAC检测
P. T. Ng, F. Rivai, A. Quah, J. C. Alag, P. K. Tan, C. Q. Chen
{"title":"Enhanced EBAC Detection on Gate Oxide Breakdown Isolation after High Voltage Electron Beam Irradiation","authors":"P. T. Ng, F. Rivai, A. Quah, J. C. Alag, P. K. Tan, C. Q. Chen","doi":"10.1109/IPFA55383.2022.9915744","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915744","url":null,"abstract":"Electron Beam (EB) irradiation with high acceleration voltage is widely reported to cause significant degradation on transistor parametric performance. Thus, low acceleration voltage EB is preferred in standard failure analysis process to minimize these unwanted transistors degradations, in the expense of poorer SEM image resolution. Unknowingly, these undesirable high voltage EB effects can be leveraged for good use to enhance the EBAC detection on Gate Oxide breakdown defects. In this paper, two successful case studies on P-type and N-type MOSFET gate oxide defect isolation were described to demonstrate this enhancement through the suppression on the gate leakage by high voltage EB induced charge trapping mechanism.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129240183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effective Defect Localization for Scan ATPG Failure through Layout Aware Analysis 基于布局感知分析的扫描ATPG故障有效缺陷定位
Jack Yi Jie Ng, Kok Heng Lau, C. N. Liew, L.L. Goh, Chia-Li Song, Lee Kean Yong
{"title":"Effective Defect Localization for Scan ATPG Failure through Layout Aware Analysis","authors":"Jack Yi Jie Ng, Kok Heng Lau, C. N. Liew, L.L. Goh, Chia-Li Song, Lee Kean Yong","doi":"10.1109/IPFA55383.2022.9915736","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915736","url":null,"abstract":"This paper presents two case studies, which are based on 10nm Field Programmable Logic Array (FPGA) technology, to highlight the approach of defect localization for scan Automated Test Pattern Generation (ATPG) failure through additional layout aware analysis, and the combination of layout study, photon emission analysis (PEM), parallel lapping, nanoprobing and Scanning Emission Microscope (SEM) inspection.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125533511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Gate oxide TDDB reliability under various stress in sub-16nm FinFET technology 亚16nm FinFET技术中栅极氧化物TDDB在各种应力下的可靠性
Xiangyu Liu, Yongsheng Sun, Junlin Huang, Xiaolu Shang, Changze Liu
{"title":"Gate oxide TDDB reliability under various stress in sub-16nm FinFET technology","authors":"Xiangyu Liu, Yongsheng Sun, Junlin Huang, Xiaolu Shang, Changze Liu","doi":"10.1109/IPFA55383.2022.9915742","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915742","url":null,"abstract":"In this work, TDDB characteristics in sub-16nm FinFET technology are investigated. The MTTF of N/PMOSFET under AC stress increases about one order of magnitude compared with the DC results under same voltage and the AC margin of N/PMOSFET are equal to 85mV and 89mV based on the fitting voltage coefficient. The TDDB characteristics under off-state stress are studied, the results indicate that the MTTF of NMOSFET in on-state and PMOSFET in off-state is lower since the majority carriers in the channel. Moreover, the dependence of on-state TDDB on Vds is studied and the results indicate that the MTTF increases first and then decreases with the increment of Vds.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122286867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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