Effective Defect Localization for Scan ATPG Failure through Layout Aware Analysis

Abstract

This paper presents two case studies, which are based on 10nm Field Programmable Logic Array (FPGA) technology, to highlight the approach of defect localization for scan Automated Test Pattern Generation (ATPG) failure through additional layout aware analysis, and the combination of layout study, photon emission analysis (PEM), parallel lapping, nanoprobing and Scanning Emission Microscope (SEM) inspection.