基于布局感知分析的扫描ATPG故障有效缺陷定位

2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2022-07-18 DOI:10.1109/IPFA55383.2022.9915736

Jack Yi Jie Ng, Kok Heng Lau, C. N. Liew, L.L. Goh, Chia-Li Song, Lee Kean Yong

{"title":"基于布局感知分析的扫描ATPG故障有效缺陷定位","authors":"Jack Yi Jie Ng, Kok Heng Lau, C. N. Liew, L.L. Goh, Chia-Li Song, Lee Kean Yong","doi":"10.1109/IPFA55383.2022.9915736","DOIUrl":null,"url":null,"abstract":"This paper presents two case studies, which are based on 10nm Field Programmable Logic Array (FPGA) technology, to highlight the approach of defect localization for scan Automated Test Pattern Generation (ATPG) failure through additional layout aware analysis, and the combination of layout study, photon emission analysis (PEM), parallel lapping, nanoprobing and Scanning Emission Microscope (SEM) inspection.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Effective Defect Localization for Scan ATPG Failure through Layout Aware Analysis\",\"authors\":\"Jack Yi Jie Ng, Kok Heng Lau, C. N. Liew, L.L. Goh, Chia-Li Song, Lee Kean Yong\",\"doi\":\"10.1109/IPFA55383.2022.9915736\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents two case studies, which are based on 10nm Field Programmable Logic Array (FPGA) technology, to highlight the approach of defect localization for scan Automated Test Pattern Generation (ATPG) failure through additional layout aware analysis, and the combination of layout study, photon emission analysis (PEM), parallel lapping, nanoprobing and Scanning Emission Microscope (SEM) inspection.\",\"PeriodicalId\":378702,\"journal\":{\"name\":\"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-07-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA55383.2022.9915736\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA55383.2022.9915736","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文介绍了两个基于10nm现场可编程逻辑阵列(FPGA)技术的案例研究，重点介绍了通过附加布局感知分析，以及结合布局研究、光子发射分析(PEM)、平行研磨、纳米探测和扫描发射显微镜(SEM)检查来定位扫描自动测试模式生成(ATPG)故障的方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Effective Defect Localization for Scan ATPG Failure through Layout Aware Analysis

This paper presents two case studies, which are based on 10nm Field Programmable Logic Array (FPGA) technology, to highlight the approach of defect localization for scan Automated Test Pattern Generation (ATPG) failure through additional layout aware analysis, and the combination of layout study, photon emission analysis (PEM), parallel lapping, nanoprobing and Scanning Emission Microscope (SEM) inspection.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

自引率

0.00%

发文量