2015 6th Asia Symposium on Quality Electronic Design (ASQED)最新文献_第3页

Non-linearity analysis of stochastic time-to-digital converter 随机时数转换器的非线性分析

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-09-24 DOI: 10.1109/ACQED.2015.7274029

V. Mikos, T. Nakura, K. Asada

引用次数: 1

Resonant power supply noise cancelling with noise detector based in DLL and vernier TDC 基于动态动态库和游标TDC的噪声检测器的谐振电源降噪

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-09-24 DOI: 10.1109/ACQED.2015.7274033

Masahiro Kano, T. Nakura, K. Asada

引用次数: 1

Compact FPGA implementation of PRESENT with Boolean S-Box 带布尔S-Box的PRESENT的紧凑FPGA实现

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-09-24 DOI: 10.1109/ACQED.2015.7274024

J. J. Tay, M. Wong, M. Wong, C. Zhang, I. Hijazin

{"title":"Compact FPGA implementation of PRESENT with Boolean S-Box","authors":"J. J. Tay, M. Wong, M. Wong, C. Zhang, I. Hijazin","doi":"10.1109/ACQED.2015.7274024","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274024","url":null,"abstract":"Ever since the conception of the ideology known as the Internet of Things (IoT), our world is slowly approaching the brink of mankind's next technological revolution. The realization of IoT requires an enormous amount of sensor nodes to acquire inputs from the connected objects. Due to the lightweight nature of these sensors, constraints emerge in the form of limited power supply and area for the implementation of information security mechanism. To ensure security in the data transmitted by these sensors, lightweight cryptographic solutions are required. In this work, our goal is to implement a compact PRESENT cipher onto a Field Programmable Gate Array (FPGA) platform. Our proposed design uses an 8-bit datapath to reduce hardware size. Instead of a traditional look-up table (LUT) based S-Box, we have implemented a Boolean S-Box through Karnaugh mapping. Further factorization is also done to reduce the size of the Boolean S-Box. As a result, we have achieved the smallest FPGA implementation of the PRESENT cipher to date, requiring only 62 slices on the Virtex-5 XC5VLX50 platform. Our design also features a respectable throughput of 51.32 Mbps at the maximum frequency of 236.574 MHz.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"1457 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127441660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 34

Automatic register balancing in model-based high-level synthesis 基于模型的高级合成中的自动寄存器平衡

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-09-24 DOI: 10.1109/ACQED.2015.7274005

C. Karfa

引用次数: 1

Energy efficient sub/near-threshold ripple-carry adder in standard 65 nm CMOS 标准65nm CMOS的高能效亚/近阈值纹波进位加法器

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-09-24 DOI: 10.1109/ACQED.2015.7273999

A. Vatanjou, T. Ytterdal, S. Aunet

{"title":"Energy efficient sub/near-threshold ripple-carry adder in standard 65 nm CMOS","authors":"A. Vatanjou, T. Ytterdal, S. Aunet","doi":"10.1109/ACQED.2015.7273999","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7273999","url":null,"abstract":"This manuscript includes chip measurements for a 32-bit Ripple-Carry Adder (“RCA”), demonstrating functionality for a supply voltage (“Vdd”) down to 84 mV. The low Vdd might be the lowest reported for comparable CMOS circuitry, not depending on special schmitt-trigger based logic or body biasing. Two 32-bit ripple-carry adders are implemented in 65 nm CMOS, having all gate lengths of 60 nm and 80 nm, respectively. The implementation having 80 nm gate lengths exploits secondary effects like the Reverse Short Channel Effect (“RSCE”) to provide lower energy per operation, compared to the 60 nm implementation, when operated down to subthreshold supply voltages. Dimensioning for symmetric noise margins, and using minority-3 circuits and inverters only, with regular layouts, contribute to the ultra low Vdd potential. According to simulations, the energy per operation could be down to about 1.5 fJ/bit for the implementation, based on L = 80 nm. For delays in the 20 ns to 110 ns range, the energy consumption for the RCA having L = 60 nm, was from 18.5 to 47 % higher than the RCA having L = 80 nm. The area was 9.7 % less for the L = 80 nm implementation, compared to the L = 60 nm RCA.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131595738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Radio-frequency silicon-based CMOS-compatible MEMS variable solenoid micro-fluidic inductor with Galinstan-based continuously-adjustable turn-ratio technique 基于galinsta连续可调转比技术的射频硅基cmos兼容MEMS可变电磁微流控电感器

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-09-24 DOI: 10.1109/ACQED.2015.7274014

Fatemeh Banitorfian, F. Eshghabadi, Asrulnizam Abd Manaf, N. Noh, M. T. Mustaffa

{"title":"Radio-frequency silicon-based CMOS-compatible MEMS variable solenoid micro-fluidic inductor with Galinstan-based continuously-adjustable turn-ratio technique","authors":"Fatemeh Banitorfian, F. Eshghabadi, Asrulnizam Abd Manaf, N. Noh, M. T. Mustaffa","doi":"10.1109/ACQED.2015.7274014","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274014","url":null,"abstract":"This paper proposes a continuously-variable MEMS solenoid inductor with resonating frequency of over 8 GHz. This inductor allows high-tuning capability for resonance adjustment purpose in reconfigurable radio-frequency circuit devices. To achieve this goal, a channel is contrived to bypass the turns of the coil through the injection of a conductive liquid (here, Galinstan). Once the number of turns decreases, the inductance value falls according to the injection level. The proposed solenoid inductor is simulated using a full-wave three-dimensional electromagnetic analysis tool, HFSS, for silicon substrate with copper metallic coil for different level of conductive liquid injection. Beside the cost-effective and easy manufacturing process, the simulation results demonstrate the 150% tuning range. The EM simulation results show a maximum quality factor of 85 at 3 GHz for proposed inductor. The minimum and maximum inductance values are 1.5 and 4 nH at 4 GHz for low-resistivity Silicon. This tunable inductor can be applied into reconfigurable radio-frequency circuits and matching networks to tune the operating frequency of the system.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123475643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An efficient buffer sizing algorithm for clock trees considering process variations 考虑进程变化的时钟树的有效缓冲区大小算法

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-09-24 DOI: 10.1109/ACQED.2015.7274017

Chao Deng, Yici Cai, Qiang Zhou, Zhuwei Chen

引用次数: 3

Cluster error correction and on-line repair for real-time TSV array 实时TSV阵列的聚类纠错与在线修复

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-09-21 DOI: 10.1109/ACQED.2015.7274022

Tsung-Chu Huang

引用次数: 0

Detection of intermittent resistive faults in electronic systems based on the mixed-signal boundary-scan standard 基于混合信号边界扫描标准的电子系统间歇性电阻性故障检测

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-08-06 DOI: 10.1109/ACQED.2015.7274011

H. Kerkhoff, Hassan Ebrahimi

引用次数: 5

Fully-hybrid computer-aided RF LNA design and evaluation for GSM-1900 standard band GSM-1900标准频段全混合计算机辅助射频LNA设计与评估

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-08-01 DOI: 10.1109/ACQED.2015.7274030

F. Eshghabadi, Fatemeh Banitorfian, N. Noh, M. T. Mustaffa, Asrulnizam Abd Manaf

引用次数: 2