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2015 6th Asia Symposium on Quality Electronic Design (ASQED)最新文献

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PrimeTime web-based report analyzer (PTWRA) tool 黄金时间基于web的报告分析器(PTWRA)工具
2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-08-01 DOI: 10.1109/ACQED.2015.7274035
F. Jumaah, Sreedharan Baskara, R. Sidek, F. Rokhani
{"title":"PrimeTime web-based report analyzer (PTWRA) tool","authors":"F. Jumaah, Sreedharan Baskara, R. Sidek, F. Rokhani","doi":"10.1109/ACQED.2015.7274035","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274035","url":null,"abstract":"In modern VLSI designs, timing closure has become a challenging and tedious task for the designers due to the fact that the number of design logic gates led to an exponential increase in the number of timing paths. PrimeTime from Synopsys is used to perform Static Timing Analysis and to generate a timing report in the form of large size text file; hence, data analysis is a complex task for the designer. This work presents a web-based text-mining software tool based on text-mining and web-based reporting techniques. It consists of two parts, the Perl software parser file in the user part, while MySQL and Apache servers in the server part. This tool parses Synopsys PrimeTime timing report and provides analysis services for team collaboration, clock skew and path constraints calculations, paths categorization and paths distribution in well-organized tables, and presents data on website pages.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114140011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Electromigration failure mechanism comparison between wafer level and package level reliability test on via structure 通孔结构晶圆级和封装级可靠性试验的电迁移失效机理比较
2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-08-01 DOI: 10.1109/ACQED.2015.7274013
W. Dulin, Ong Cheng Nee, N. H. Seng
{"title":"Electromigration failure mechanism comparison between wafer level and package level reliability test on via structure","authors":"W. Dulin, Ong Cheng Nee, N. H. Seng","doi":"10.1109/ACQED.2015.7274013","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274013","url":null,"abstract":"Wafer level reliability (WLR) and package level reliability (PLR) test methods are widely used for Electromigration (EM) accelerated lifetime test. Both methods on different via structures are studied in this paper. The experimental result shows single via terminated EM structure lifetime is comparable between WLR and PLR methods based on Black's equation; while stack via terminated structure lifetime is not homogeneous between the two methods. Physical failure analysis (PFA) also shows different failure mechanisms between WLR and PLR methods on stack via terminated structure. The hypothesis is that during WLR test, large joule heating is produced at stack via area due to W-via high resistivity. The temperature even is high enough to make the aluminum between stack vias melt or burnt out.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123650804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
3-D global routing with layer directive and scenic constraints 具有层指令和场景约束的三维全局路由
2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-08-01 DOI: 10.1109/ACQED.2015.7274018
Zhongdong Qi, Yici Cai, Qiang Zhou, Zhuwei Chen
{"title":"3-D global routing with layer directive and scenic constraints","authors":"Zhongdong Qi, Yici Cai, Qiang Zhou, Zhuwei Chen","doi":"10.1109/ACQED.2015.7274018","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274018","url":null,"abstract":"As technology advances, modern physical synthesis flows pose layer directive and scenic constraints to global routing. Respecting these constraints in global routing is critical to achieve timing closure. In this paper, we propose a 3-D global routing algorithm which simultaneously respects layer directive constraints and scenic constraints. The routing algorithm is based on iterative ripping-up and rerouting. The core components of the algorithm include a 3-D A* search which strictly obeys given constraints, and a net ordering approach which helps to achieve high-quality routing results. Experimental results demonstrate the effectiveness of the routing algorithm.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128960903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An on-chip transfer function measurement of PLLs with triangular modulated stimulus 带三角形调制刺激的锁相环片上传递函数测量
2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-08-01 DOI: 10.1109/ACQED.2015.7274034
T. Kikkawa, T. Nakura, K. Asada
{"title":"An on-chip transfer function measurement of PLLs with triangular modulated stimulus","authors":"T. Kikkawa, T. Nakura, K. Asada","doi":"10.1109/ACQED.2015.7274034","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274034","url":null,"abstract":"This paper proposes an on-chip measurement method of PLL transfer function. In our proposed scheme, we modulated the phase of the PLL input in triangular form using Digital-to-Time Converter (DTC) and read out the response by Time-to-Digital Converter (TDC). Combination of the DTC and TDC can obtain the transfer function of the PLL both in the amplitude domain and the phase domain. Since the DTC and TDC can be controlled and observed by digital signals, the measurement can be conducted without any high speed analog signal. Moreover, since the DTC and TDC can be designed symmetrically, the measurement method is robust against PVT variations. MATLAB simulation results demonstrated the measurement of the transfer function.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121316759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Testing power-delivery TSVs 测试供电tsv
2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-08-01 DOI: 10.1109/ACQED.2015.7274021
Hua-Xuan Li, H. Fu, Shi-Yu Huang, Jin-Cheng Jiang, D. Kwai, Yung-Fa Chou
{"title":"Testing power-delivery TSVs","authors":"Hua-Xuan Li, H. Fu, Shi-Yu Huang, Jin-Cheng Jiang, D. Kwai, Yung-Fa Chou","doi":"10.1109/ACQED.2015.7274021","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274021","url":null,"abstract":"Many TSVs in a 3D IC are not used for signal transmission but for power delivery. Techniques needed to detect them have not been studied in-depth in the literature. In this paper, we present a test method for power-delivery TSVs, by embedding ring-oscillator (RO) based monitors (in a scalable architecture) to detect if there is any excessive voltage-drop at the end of any TSV during a manufacturing test session. One key feature as opposed to previous RO-based methods is that our approach is able to detect the worst-case dynamic voltage-drop (occurring in a very short period of time such as 1ns), rather than just the average voltage-drop over a long period of time. This is essential in order to detect small defects inside the power delivery network. These defects, if not detected, could set off a transient timing failure when the IC is operated in a system.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127095048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A field-based parasitic capacitance model with 3-D terminal and terminal fringe components 具有三维终端和终端边缘分量的基于场的寄生电容模型
2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-08-01 DOI: 10.1109/ACQED.2015.7274028
Aixi Zhang, Wei Zhao, Yue Hu, Jin He, Qingxing He, Lei Song, Haiqin Zhou, Yong Wu
{"title":"A field-based parasitic capacitance model with 3-D terminal and terminal fringe components","authors":"Aixi Zhang, Wei Zhao, Yue Hu, Jin He, Qingxing He, Lei Song, Haiqin Zhou, Yong Wu","doi":"10.1109/ACQED.2015.7274028","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274028","url":null,"abstract":"In this paper, a parasitic capacitance model for a single three-dimensional (3-D) wire above a plate is developed. The model decomposes electric field into various regions and gives solutions to each part. The total capacitance is the summation of all capacitance parts corresponding to the electric field distribution. The model's physical base minimizes its complexity and error comparing to a traditional empirical fitting process. Verified by extensive COMSOL simulations, the model can accurately predict parasitic capacitance for a wide range of BEOL wire dimensions. Thus, it holds potential to be further investigated for circuit simulation and design.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133999579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A new 600V partial SOI LDMOS with step-doped drift region 一种新的600V阶跃掺杂漂移区部分SOI LDMOS
2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-08-01 DOI: 10.1109/ACQED.2015.7274027
Yue Hu, Hao Wang, Caixia Du, Yuzhun Du, Peigang Deng, Jin He, Lei Song, Haiqin Zhou, Yong Wu
{"title":"A new 600V partial SOI LDMOS with step-doped drift region","authors":"Yue Hu, Hao Wang, Caixia Du, Yuzhun Du, Peigang Deng, Jin He, Lei Song, Haiqin Zhou, Yong Wu","doi":"10.1109/ACQED.2015.7274027","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274027","url":null,"abstract":"A new 600V Partial Silicon-on-Insulator (PSOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with step-doped drift region (SDD) is introduced to improve breakdown voltage (BV) and reduce on-resistance (Ron). The step-doped profile induces an electric field peak in the surface of the device, which can improve the surface field distribution and the doping accommodation in the drift region. The adjusted drift region can allow higher doping concentration under the drain end which results in higher breakdown voltage, and accommodate more impurity atoms as a whole which provides more electrons to support higher current and thus reduce on-resistance. The proposed LDMOS transistor with SDD in partial PSOI (SDD-PSOI) is analyzed by 2-D numerical simulations, compared with conventional SOI (CSOI) and conventional PSOI (CPSOI) LDMOS transistors. The results indicate that the proposed structure can significantly improve BV up to 607V and reduce on-resistance by 12.6% in comparison to CPSOI.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133310626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High voltage MOS modeling with BSIM4 sub-circuit model 用BSIM4子电路模型进行高压MOS建模
2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-08-01 DOI: 10.1109/ACQED.2015.7274026
Chiew Ching Tan, P. Tan
{"title":"High voltage MOS modeling with BSIM4 sub-circuit model","authors":"Chiew Ching Tan, P. Tan","doi":"10.1109/ACQED.2015.7274026","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274026","url":null,"abstract":"This paper presents a technique for modeling high-voltage MOS (HVMOS) devices with BSIM4 sub-circuit model. Two voltage-dependent resistors, rd and rs are added into the drain and source side of a core BSIM4 model to capture the high voltage effects; quasi-saturation (QS) and self-heating effect (SHE). We use rd to capture QS. The voltage drop across rd captures the actual physical effect that causes QS. To model SHE, we use a new empirical method. Rs is used to ensure the effective drain-to-source voltage (Vds_eff) and effective gate-to-source voltage (Vgs_eff) drop about the same amount at saturation point. Hence, the saturation point remained unchanged. When Vds further increases after the saturation point, the Vd drop across rs is larger and reduces Id further. This causes an effect similar to SHE. By applying the proposed methodology, we are able to fit the silicon data. We also discuss the methodology to model the SHE dynamic effect by introducing a capacitor (cs) in parallel with rs. When Vd pulse is applied at the Vd, cs is being charged and almost no current flowing through rs. Hence, no SHE at that time. When cs is fully charged, then rs takes effect. This captures the dynamic characteristics of SHE.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127296005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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