Aixi Zhang, Wei Zhao, Yue Hu, Jin He, Qingxing He, Lei Song, Haiqin Zhou, Yong Wu
{"title":"具有三维终端和终端边缘分量的基于场的寄生电容模型","authors":"Aixi Zhang, Wei Zhao, Yue Hu, Jin He, Qingxing He, Lei Song, Haiqin Zhou, Yong Wu","doi":"10.1109/ACQED.2015.7274028","DOIUrl":null,"url":null,"abstract":"In this paper, a parasitic capacitance model for a single three-dimensional (3-D) wire above a plate is developed. The model decomposes electric field into various regions and gives solutions to each part. The total capacitance is the summation of all capacitance parts corresponding to the electric field distribution. The model's physical base minimizes its complexity and error comparing to a traditional empirical fitting process. Verified by extensive COMSOL simulations, the model can accurately predict parasitic capacitance for a wide range of BEOL wire dimensions. Thus, it holds potential to be further investigated for circuit simulation and design.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"272 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A field-based parasitic capacitance model with 3-D terminal and terminal fringe components\",\"authors\":\"Aixi Zhang, Wei Zhao, Yue Hu, Jin He, Qingxing He, Lei Song, Haiqin Zhou, Yong Wu\",\"doi\":\"10.1109/ACQED.2015.7274028\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a parasitic capacitance model for a single three-dimensional (3-D) wire above a plate is developed. The model decomposes electric field into various regions and gives solutions to each part. The total capacitance is the summation of all capacitance parts corresponding to the electric field distribution. The model's physical base minimizes its complexity and error comparing to a traditional empirical fitting process. Verified by extensive COMSOL simulations, the model can accurately predict parasitic capacitance for a wide range of BEOL wire dimensions. Thus, it holds potential to be further investigated for circuit simulation and design.\",\"PeriodicalId\":376857,\"journal\":{\"name\":\"2015 6th Asia Symposium on Quality Electronic Design (ASQED)\",\"volume\":\"272 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 6th Asia Symposium on Quality Electronic Design (ASQED)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ACQED.2015.7274028\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACQED.2015.7274028","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A field-based parasitic capacitance model with 3-D terminal and terminal fringe components
In this paper, a parasitic capacitance model for a single three-dimensional (3-D) wire above a plate is developed. The model decomposes electric field into various regions and gives solutions to each part. The total capacitance is the summation of all capacitance parts corresponding to the electric field distribution. The model's physical base minimizes its complexity and error comparing to a traditional empirical fitting process. Verified by extensive COMSOL simulations, the model can accurately predict parasitic capacitance for a wide range of BEOL wire dimensions. Thus, it holds potential to be further investigated for circuit simulation and design.