2015 6th Asia Symposium on Quality Electronic Design (ASQED)最新文献_第2页

MIM capacitance efficiency study for high speed I/O power integrity network design: MIM and MIMless high speed I/O performance characterization 高速I/O电源完整性网络设计的MIM电容效率研究:MIM和MIMless高速I/O性能表征

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-09-24 DOI: 10.1109/ACQED.2015.7274010

F. Tan, Ming Dak Chai, Mohamad Shahrir bin Tamrin

引用次数: 0

Optimizing test time for core-based 3-D integrated circuits by genetic algorithm 用遗传算法优化基于核的三维集成电路测试时间

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-09-24 DOI: 10.1109/ACQED.2015.7274008

Tanusree Kaibartta, C. Giri, H. Rahaman, D. K. Das

引用次数: 2

Clock gating assertion check: An approach towards achieving faster verification closure on clock gating functionality 时钟门控断言检查:一种在时钟门控功能上实现更快的验证关闭的方法

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-09-24 DOI: 10.1109/ACQED.2015.7274015

W. Zhong, N. Noh, B. A. Rosdi

{"title":"Clock gating assertion check: An approach towards achieving faster verification closure on clock gating functionality","authors":"W. Zhong, N. Noh, B. A. Rosdi","doi":"10.1109/ACQED.2015.7274015","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274015","url":null,"abstract":"Clock gating is a power reduction technique widely used in Register Transfer Level (RTL) stage of a chip design. The addition of clock gating logics has increased the complexity of a design and therefore requires considerable amount of verification effort. Furthermore, the scoreboard checking mechanism in Open Verification Methodology (OVM) verification environment still lacks the capability to completely comprehend the checking of clock gating logics correctness. To address this, a verification method, called Clock Gating Assertion Check (CGAC) method, independent of verification environment is proposed aiming at achieving a faster pre-silicon verification closure on clock gating logics with minimum verification effort. The proposed method is an automated flow using codes written in Hardware Description Language (HDL) in RTL stage and clock domains information of a design as the main inputs to generate checks at possible clock gating boundary conditions. The CGAC method was used to verify the clock gating logics of an existing Soft Intellectual Property (SIP) design. The implementation details of the method are discussed in this paper. By using the method, a total of 4 clock gating bugs were found and analysis on the impacts of the bugs is discussed. As a conclusion, the proposed method is proven effective in ensuring the correct clock gating implementation in a design.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121611041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A wide input voltage range start-up circuit for solar energy harvesting system 一种用于太阳能收集系统的宽输入电压范围启动电路

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-09-24 DOI: 10.1109/ACQED.2015.7274031

Shourya Kansal, A. Mantha, Y. B. Priyamvada, G. Chowdary, S. G. Singh, A. Dutta

引用次数: 3

An accurate detailed routing routability prediction model in placement 一种准确详细的布线可达性预测模型

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-09-24 DOI: 10.1109/ACQED.2015.7274019

Quan Zhou, Xueyan Wang, Zhongdong Qi, Zhuwei Chen, Qiang Zhou, Yici Cai

引用次数: 44

SynDFG: Synthetic dataflow graph generator for high-level synthesis SynDFG:用于高级合成的合成数据流图生成器

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-09-24 DOI: 10.1109/ACQED.2015.7274006

Sharad Sinha, Wei Zhang

{"title":"SynDFG: Synthetic dataflow graph generator for high-level synthesis","authors":"Sharad Sinha, Wei Zhang","doi":"10.1109/ACQED.2015.7274006","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274006","url":null,"abstract":"Dataflow graphs obtained from benchmark applications depend on the compiler used and its settings. This makes comparison of results in high level synthesis research using such dataflow graphs difficult. Therefore, a synthetic dataflow graph generator for generating dataflow graphs of any size from a few tens of nodes to thousands of nodes for research in high level synthesis is presented. The user has the flexibility to specify number of nodes and set node attributes like node type (operation type), in-degree and the maximum and the minimum parallelism in each control step. The generated dataflow graphs can be used for research in scheduling, allocation and hardware binding. Sharing of input parameters among researchers will allow generation of identical synthetic graphs on identical platforms thus facilitating easier and more meaningful comparison of results. The concept of \"Biased Dataflow Graphs (BDFG)\" is introduced where operations of certain types are large in number. These provide the required granularity in operations, exploitation of inherent parallelism and option to explore the area space in modern FPGAs consisting of LUTs, BRAMs and DSP slices. The generated graphs overcome these limitations in the two existing methods: Task Graphs for Free (TGFF) and Synchronous Dataflow Graphs for Free (SDF3).","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"330 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122743247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design for reliablity: A novel counter matrix code for FPGA based quality applications 可靠性设计:一种基于FPGA的高质量应用的新型计数器矩阵代码

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-09-24 DOI: 10.1109/ACQED.2015.7274007

Ahilan Appathurai, P. Deepa

引用次数: 17

A pipelined CORDIC architecture and its implementation in all-digital FM modulator-demodulator 一种流水线化的CORDIC结构及其在全数字调频解调器中的实现

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-09-24 DOI: 10.1109/ACQED.2015.7274004

T. Adiono, Nur Ahmadi, Antonius P. Renardy, A. Fadila, Naufal Shidqi

引用次数: 4

Architectural error prediction using probabilistic error masking matrices 使用概率错误屏蔽矩阵的架构错误预测

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-09-24 DOI: 10.1109/ACQED.2015.7274003

Z. Wang, Hui Xie, S. Chafekar, A. Chattopadhyay

引用次数: 2

On enhancing the reliability of digital microfluidic biochips (DMFB) through electrode cells health classification 通过电极细胞健康分类提高数字微流控生物芯片可靠性的研究

2015 6th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2015-09-24 DOI: 10.1109/ACQED.2015.7274032

M. A. Sheikh, N. Ali, N. H. Hamid, F. Hussin, V. Shukla

引用次数: 4