2019 International Wafer Level Packaging Conference (IWLPC)最新文献

{"title":"Semiconductor-On-Polymer the Evolution of thin IC Packaging","authors":"D. Hackler, E. Prack","doi":"10.23919/IWLPC.2019.8914105","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914105","url":null,"abstract":"IC packages are getting thinner to facilitate thinner systems. Labels and tags are getting smarter. Electronics are starting to bend, and reliability is in question. Semiconductor-on-Polymer (SoP) Chip Scale Packaging (CSP) is an enabling technology that can reliably integrate packaged ICs in flexible electronics. SoP™ is being used to produce the leading edge of high performance ultra-thin flexible hybrid electronics and sensors today. Chip Scale Packaging (CSP) defines the logical end of IC package scaling in 2D surface area as package area and IC size converge. Scaling thickness is a key metric in further packaging evolution. SoP CSP provides a path to the end of IC package scaling in 3D volume by reducing package thicknesses to less than what is generally regarded as ultra-thin for bare die. The result is feasibility for packaged ICs to be utilized in direct chip attach (DCA) applications. Die thickness is a key contributor to DCA and FC-BGA IC package thickness. SoP replacement of bare die in conventional IC packaging is envisioned to facilitate package thickness reduction and improved reliability for FC-BGA packages, 3D and heterogeneous integration. This presentation introduces SoP technology and describes SoP CSP direct interconnect (DI) assembly that has progressed from 24-pin attachment to System-on-Chip assembly of DI pitch at ≤100um in flexible hybrid electronics. The presentation also shows the technology roadmap for SoP application to IC packaging and how SoP may fit into current IC packaging roadmaps.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129010061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Growing Application Field of Laser Debonding: From Advanced Packaging to Future Nanoelectronics","authors":"A. Phommahaxay, G. Beyer, I. Radu, E. Beyne, Alice Guerrero, Luke Prenger, K. Yess, Kim Arnold, Sebastian Tussing, W. Spiess, Thomas Rapps, K. Kennes, S. Lutter, A. Podpod, S. Brems, J. Slabbekoorn, E. Sleeckx, C. Huyghebaert, I. Asselberghs, Andy Miller","doi":"10.23919/IWLPC.2019.8914124","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914124","url":null,"abstract":"Thin substrate handling has become one of the cornerstone technologies that enabled the development of 3D stacked ICs over the past years. Temporary wafer bonding has continuously improved and reached the maturity level required by volume manufacturing of first-generation devices. Yet the need remains for further development and performance increases. Indeed, the continuous push for denser interconnects has brought new requirements for a through-silicon-via technology on one side but also pushed temporary adhesive and carrier technology into the space of wafer reconstruction and fan-out WLP. On the opposite side of the semiconductor spectrum, at the early steps of the front-end-of-line processing, transistor scaling becomes more and more challenging, including demanding the integration of higher numbers of novel materials. To further increase the options of materials, a growing number of exploratory devices are considering using a layer transfer approach. The advances in temporary bonding and debonding technology is bringing the packaging and nanoscale world together.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126863190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improved Semiconductor Device Reliability from Plasma Dicing","authors":"R. Barnett, J. Hopkins, S. Fulton, O. Ansell, S. Kazemi, M. Day","doi":"10.23919/IWLPC.2019.8913904","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8913904","url":null,"abstract":"There are many emerging applications where die strength is critically important, most notably in harsh automotive environments, but also in other areas such as consumer wearables or remote sensing. Plasma dicing using a dry, chemically-driven etch has been introduced into production applications as a viable alternative to traditional methods of wafer dicing, using mechanical saws or LASER based approaches. Both of these conventional techniques create sufficient damage in the silicon as to fundamentally weaken the die. There are, of course, ways to mitigate against this damage, usually at the expense of throughput, but no solution will eliminate the damage these methods cause. The chips and cracks that exist in every die separated by these means could propagate causing a catastrophic failure, with the growth of the fracture accelerated by the external forces. Further benefits of Plasma dicing include a particle free result that is particularly important where die-to-die, or die-to-wafer bonding takes place. Designers can also access non-orthogonal layouts and form factors, with consistent device appearance minimizing inspection demands. Plasma dicing can contribute significantly to improved device reliability and provide positive outcomes for manufacturing yield and costs. This paper will describe factors that have been investigated to enable successful integration of plasma dicing into existing process routes, such as dicing tape compatibility, optimized laser grooving to prepare dicing streets, and post-dicing surface treatments.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121426590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Resolution Automatic X-Ray Inspection for Continuous Monitoring of Advanced Package Assembly","authors":"Scott J. Jewler","doi":"10.23919/IWLPC.2019.8914113","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914113","url":null,"abstract":"At the same time that IC packaging interconnect is being driven towards higher density and more solder connections, the market's tolerance for defective materials is rapidly disappearing. Existing techniques for inspecting solder joints inside of packages such as cross sectioning and conventional high-resolution X-ray are time consuming and impractical for 100% monitoring and process feedback. A novel X-ray system architecture combined with advanced machine learning algorithms enables high speed automated inspection of complex IC package structures. Just as Automated Optical Inspection (AOI) has been widely deployed for visible structures and Automated X-ray Inspection (AXI) for Ball Grid Array solder joints, High Resolution Automated X-ray inspection (HR-AXI) brings inline inspection to fine pitch flip chip solder joint assembly processes. HR-AXI delivers orders of magnitude higher inspection speeds with greater sensitivity than conventional point projection X-ray systems. Device damage is reduced as a result of shorter exposure times and an optimized system configuration. Using single top down images, advanced machine learning algorithms rapidly find defects such as non-wets, voids, and bridges.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116757579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Recent Developments in Fine Pitch Wafer-To-Wafer Hybrid Bonding with Copper Interconnect","authors":"J. Theil, L. Mirkarimi, G. Fountain, Guilian Gao, R. Katkar","doi":"10.23919/IWLPC.2019.8913862","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8913862","url":null,"abstract":"3D architectures are increasingly making their way into commercial products such as image sensors and 3D memory. While hybrid bonding exists today in wafer-to-wafer (W2W) format in high volume manufacturing, the proliferation of this technology continues to accelerate. A wide range of new products may be considered by leveraging the ability to connect circuit elements fabricated with two different process technologies. For example, some NAND architectures are monolithic 3D devise which are formed using processes with divergent thermal requirements such as the high temperature memory technology and the lower temperature logic. This monolithic approach is the standard today but leads to a final product that is a compromise of the thermal budget constraints. Alternatively, disaggregation of the memory components and the logic components onto separate wafers would allow each technology to be optimized independently with potentially different thermal budgets. Using Cu based hybrid bonding, a fine pitch Cu interconnect may be used to then join the two wafers at temperatures well below 400°C while achieving superior I/O performance within a smaller footprint [1]. Direct Bond Interconnect (DBI®) technology, is a low temperature hybrid bonding process that forms a dielectric-to-dielectric bond at room temperature and a metal-to-metal bond at the appropriately designed temperature. It is the key enabling technology for advanced products because of its unique ability to bond wafers at low temperature and to successfully bond pads ranging from $1.9 mu mathrm{m}$ to $15 mu mathrm{m}$ diameter. The corresponding pitches range from $3.8 mu mathrm{m}$ to 40 um. Generally, a low temperature anneal process of 150–400°C can be achieved. The all-Cu interconnect across the bond interface provides good electrical performance and enhanced reliability. [2] This paper presents bonding and electrical yield results with a test vehicle design that demonstrates high-density, fine pitch bonding with high-yield. The test vehicle consists of daisy chain test patterns with $4 mu mathrm{m}$ bonding pitch with 115k links and covers a bond area of 3.61 mm2. The process flow enables high throughput processing with room temperature bonding and post-bond batch anneal. The process shows minimum electrical yield greater than 98% across all wafers. Longer chains of 500k links with a $3 mu mathrm{m}$ diameter pad with a $10 mu mathrm{m}$ pitch show similar yields. Temperature cycling and autoclave tests of the $3 mu mathrm{m}$ diameter pad test structures showed a robust Cu/Cu interconnection and superior reliability performance.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"275 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134032729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Defect-Free Electroplating of High Aspect Ratio Through Silicon Vias: Role of Size and Aspect Ratio","authors":"C. A. Joshi, H. Ramanarayan, K. Khoo, H. Jin, S. Quek, D. T. Wu, N. Sridhar, M. S. Bharathi","doi":"10.23919/IWLPC.2019.8914019","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914019","url":null,"abstract":"We study the role of via size and aspect ratio in defect-free electroplating of through silicon vias in 3DICs. Using a level-set curvature enhanced adsorbate coverage model, we simulate the electroplating of vias of various sizes and aspect ratio by varying the overpotential and the initial copper concentration. We find that as the via size and aspect ratio increases, the filling fraction reduces and voids are formed in the vias. Increasing overpotential also reduces the filling fraction. We show that in all these cases, increasing the initial copper concentration can result in increased filling of the vias of higher aspect ratios.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124468191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Novel Temporary Bonding and Debonding Solutions Enabling an Ultrahigh Interonnect Density Fo-Wlp Structure Assembly with Quasi-Zero Die Shift","authors":"A. Podpod, Andy Miller, G. Beyer, E. Beyne, Alice Guerrero, Xiao Liu, Qi Wu, K. Yess, Kim Arnold, A. Phommahaxay, P. Bex, K. Kennes, J. Bertheau, H. Arumugam, T. Cochet, K. Rebibis, E. Sleeckx","doi":"10.23919/IWLPC.2019.8914144","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914144","url":null,"abstract":"Next-generation temporary bonding adhesive material is introduced into imec's high interconnect density flip chip on fan-out wafer-level package (FC FOWLP) concept [1], [2]. After molding on silicon substrates, an ultralow die shift with an average of $< 2mu mathrm{m}$ die-to-carrier mismatch and warpage of $< 200mu mathrm{m}$ were achieved in a full 300-mm wafer. These values are orders of magnitude improvement over results reported in literature and has major implications on the processing of overmolded substrates. The combination of this low warp and ultralow distortion opens the possibility for fine-pitch RDL combined with a chip-first approach, which was impossible until now. The evolution of warpage and die shift through multiple processing steps will also be discussed in this paper.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122303040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Shift-Left Vertification in HDAP Design","authors":"Chris Cone, Keith Felton, K. Rinebold, J. Ferguson","doi":"10.23919/IWLPC.2019.8914101","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914101","url":null,"abstract":"High Density Advanced Package Design – or HDAP – continues to show remarkable advantages over monolithic SoC. Foundries and OSATs are teaming to provide manufacturing capabilities including FOWLP and various derivatives suitable for RF, IoT, automotive and mobile products or SI 3D 3DIC designs typically used in today's advanced memory and GPU/CPU applications. As HDAP manufacturing advances, so does design complexity requiring clearly defined and understood design methodologies. After providing an analysis the key steps to perform complex HDAP design including component aggregation, assembly and system optimization and design verification, this paper will highlight the requirement for a “shift-left” design environment where verification steps including LVS & LVL, thermal, power and signal integrity are performed interactively during the system integration and optimization and not left to after design completion.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129135893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"[Copyright notice]","authors":"","doi":"10.23919/iwlpc.2019.8913976","DOIUrl":"https://doi.org/10.23919/iwlpc.2019.8913976","url":null,"abstract":"","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132395133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Overview About the Excimer Laser Ablation of Different Polymers and Their Application for Wafer and Panel Level Packaging","authors":"R. Gernhardt, M. Wöhrmann, Friedrich Müller, K. Hauck, M. Töpper, K. Lang, H. Hichri, M. Arendt","doi":"10.23919/IWLPC.2019.8914117","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914117","url":null,"abstract":"The demands for packaging for either wafer or panel respectively heterogeneous integration in general are rising. New materials and technologies are needed to address the challenges resulting from that demands like better dielectric properties or higher resolution just to name two examples. The excimer laser ablation is able to meet that needs and process the new materials, which are not always photosensitive anymore. The system used for this paper is a combination of a projection stepper platform combined with an excimer laser. The field of application for this system is quite wide. It can be used for laser de-bonding of supporting substrates or the seed layer removal after galvanic. The main application, however, is the ablation of all types of polymers to generate VIAs for example. In contrast to already known PCB lasers, it is also possible to ablate complex structures in parallel, as it is a mask-based technology. Due to that, it is possible to generate trenches and VIAs within one step. This enables a technology already known from the front end of line (FEOL) to be transferred to the back end of line (BEOL): the dual damascene process. Within this paper, all the mentioned applications and the experience with a broad variety of polymer materials such as Polyimide, PBO, BCB, ABF, Dry Films are going to be presented. It is going to be shown that the excimer laser system can overcome the limitations of common polymers in terms of resolution and that the laser dual damascene approach can meet the needs for the overall demand towards 2um lines and space for packaging. Additionally some reliability data is presented that prove that the laser ablation can replace the today common lithography processes without any drawbacks.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116177773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}