A. Phommahaxay, G. Beyer, I. Radu, E. Beyne, Alice Guerrero, Luke Prenger, K. Yess, Kim Arnold, Sebastian Tussing, W. Spiess, Thomas Rapps, K. Kennes, S. Lutter, A. Podpod, S. Brems, J. Slabbekoorn, E. Sleeckx, C. Huyghebaert, I. Asselberghs, Andy Miller
{"title":"The Growing Application Field of Laser Debonding: From Advanced Packaging to Future Nanoelectronics","authors":"A. Phommahaxay, G. Beyer, I. Radu, E. Beyne, Alice Guerrero, Luke Prenger, K. Yess, Kim Arnold, Sebastian Tussing, W. Spiess, Thomas Rapps, K. Kennes, S. Lutter, A. Podpod, S. Brems, J. Slabbekoorn, E. Sleeckx, C. Huyghebaert, I. Asselberghs, Andy Miller","doi":"10.23919/IWLPC.2019.8914124","DOIUrl":null,"url":null,"abstract":"Thin substrate handling has become one of the cornerstone technologies that enabled the development of 3D stacked ICs over the past years. Temporary wafer bonding has continuously improved and reached the maturity level required by volume manufacturing of first-generation devices. Yet the need remains for further development and performance increases. Indeed, the continuous push for denser interconnects has brought new requirements for a through-silicon-via technology on one side but also pushed temporary adhesive and carrier technology into the space of wafer reconstruction and fan-out WLP. On the opposite side of the semiconductor spectrum, at the early steps of the front-end-of-line processing, transistor scaling becomes more and more challenging, including demanding the integration of higher numbers of novel materials. To further increase the options of materials, a growing number of exploratory devices are considering using a layer transfer approach. The advances in temporary bonding and debonding technology is bringing the packaging and nanoscale world together.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International Wafer Level Packaging Conference (IWLPC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/IWLPC.2019.8914124","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Thin substrate handling has become one of the cornerstone technologies that enabled the development of 3D stacked ICs over the past years. Temporary wafer bonding has continuously improved and reached the maturity level required by volume manufacturing of first-generation devices. Yet the need remains for further development and performance increases. Indeed, the continuous push for denser interconnects has brought new requirements for a through-silicon-via technology on one side but also pushed temporary adhesive and carrier technology into the space of wafer reconstruction and fan-out WLP. On the opposite side of the semiconductor spectrum, at the early steps of the front-end-of-line processing, transistor scaling becomes more and more challenging, including demanding the integration of higher numbers of novel materials. To further increase the options of materials, a growing number of exploratory devices are considering using a layer transfer approach. The advances in temporary bonding and debonding technology is bringing the packaging and nanoscale world together.