2019 International Wafer Level Packaging Conference (IWLPC)最新文献

{"title":"The Latest in XRF Coatings Analysis Equipment for Micro-Scale Semiconductor Packaging","authors":"Matt Kreiner, M. Ohgaki, K. Shinohara","doi":"10.23919/IWLPC.2019.8914056","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914056","url":null,"abstract":"X-ray fluorescence (XRF) analysis is a widely used technique to measure plating thickness. Its main advantage resides in allowing simultaneous, non-destructive analysis of multilayered plated parts. The miniaturization and increasing complexity of electronic devices proliferated by advancements in smartphone functionality continues with the rise of microelectromechanical systems (MEMS). Consequently, the electronic components and features for these devices are becoming as miniscule as ever. In order to maintain the necessary quality of these components, the measuring and control of the plating thickness and composition is critical. For this application, an XRF plating thickness analyzer capable of high accuracy measurement in small areas is essential. Utilizing the latest X-ray focusing polycapillary technology with a high-sensitivity detector, modern XRF systems deliver high-precision measurements of nanometer-scale plating. The beam diameter of less than $20 mu mathrm{m}$ (full width at half maximum, FWHM) not only allows plating thickness measurements, but also composition analysis, useful for solder bumps. This allows for an outstanding measurement repeatability, achieving precision of 1% RSD for gold plating at 100 Å. Furthermore, the levels of irradiated energy are lower than those utilized in wavelength dispersive techniques (WDXRF), thus considerably reducing the potential damage to the sample. This paper discusses XRF as an analytical technique for determining the thickness of plated or coated layers applied to a substrate. The effects of layer structure and properties on multilayer XRF thickness measurements are investigated.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"679 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116107048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Functional Inkjet Printing Equipment: A Set of Features Leading to Productive Results","authors":"L. Gautero, S. Donkers, W. Brok","doi":"10.23919/IWLPC.2019.8914146","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914146","url":null,"abstract":"The economic advantages of accurate patterning with inkjet printing are relevant for the semiconductor market. Mature inkjet printers for high volume production and established development procedures are available. Strategies and solutions of functional inkjet printing technology are presented to reduce the time to market. Common applications will be named and illustrated. The features of printers and their general components will be described in detail. Emphasis will be given to specific digitally-enabled features. Furthermore, the professional use of functional inkjet printing is presented with typical cases. The demonstration of how nozzle performances, printing clearances and solidification mechanism are quantified and brought in control is given. The growing acceptance from the semiconductor market proves the relevance of inkjet printing features for production and innovation needs.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114438882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Panel Level Packaging for Component Integration of an Energy Harvesting System","authors":"T. Braun, K. Lang, R. Kahle, S. Voges, O. Hölck, J. Bauer, K. Becker, R. Aschenbrenner, M. Dreissigacker, M. Schneider-Ramelow","doi":"10.23919/IWLPC.2019.8914021","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914021","url":null,"abstract":"Within the European funded project smart-MEMPHIS the goal was to tackle the main challenge for all smart devices – self-powering. The project was aimed to design, manufacture and test a miniaturized autonomous energy supply based on harvesting vibrational energy with piezo-MEMS energy harvesters. Cost effective packaging was needed for 3D system integration of a MEMS-based multi-axis energy harvester, an ultra-low-power ASIC to manage the variations of the frequency and harvested power, and a miniaturized energy storing supercapacitor. Miniaturization was another key demand as target applications were a leadless pacemaker and a wireless sensor network for structural health monitoring. Panel Level Packaging (PLP) was selected as packaging technology for the harvester components. A basic study on the embedding of piezo-MEMS harvester has been performed as well as the development and proof of concept of a new PLP based supercapacitor housing. For the power management unit an ASIC together with two capacitors have been integrated by Fan-out Panel Level Packaging (FOPLP). Material selection and process development was first done on wafer level size and then transferred to large area 457x305 mm2 panel size. Main focus was here to find a suitable material combination and process parameters for the embedding of SMD capacitors together with bare dies in a fan-out panel level package. A technology study has been performed to analyze the influence of SMD component size and pitch, thermal release tape and epoxy molding compound type during compression molding. Results have used to finally select materials for prototype built. Reliability testing have been performed to prove the overall concept and material selection for PLP.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122077829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enabling Heterogeneous Integration for Next Generation Fan-Out Applications Using Full-Field Projection Scanning","authors":"Fabian Benthaus, William Vis, H. Hichri, M. Arendt","doi":"10.23919/IWLPC.2019.8913963","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8913963","url":null,"abstract":"The demand for higher functionality devices drives integration technologies in the third dimension to overcome limitations in Moore's Law. One popular example for 3D Integration is Package-on-Package (PoP), where memory stacks are mounted above the processor. Heterogeneous Integration (HI) is one of the key technologies to meet future fan-out (FO) application standards using higher bandwidths and higher chip-to-chip interconnection density or IO density. However, HI brings new challenges like large-area panel production and design limitations. Fast increasing package size in combination with insufficient increase in stepper reticle size is inhibiting designs for large packages and HI applications. A solution which provides limitless design and fine resolution patterning capabilities is a full-field projection scanner. For next generation FO applications, a projection scanner provides superior performance compared to a stepper by enabling limitless design, allowing dies of any size and patterning of non-repeated features at higher throughput and lower cost. This paper presents technical challenges and provides solutions for future HI FO applications, using a full-field exposure system for large package integration, eliminating low yielding stitching steps. High accuracy overlay, fine resolution for RDL routing and large depth of focus (DOF) for thick resist applications with high aspect ratio is demonstrated. The extendibility to large panel packaging integration is discussed.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129830604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wave Front Phase Imaging of Wafer Geometry Using High Pass Filtering for Improved Resolution","authors":"J. Trujillo-Sevilla, J. Ramos-Rodríguez, J. Gaudestad","doi":"10.23919/IWLPC.2019.8914114","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914114","url":null,"abstract":"In this paper we show that Wave Front Phase Imaging (WFPI) has good enough lateral resolution and is sensitive enough to measure roughness on a silicon wafer by simply acquiring a simple image of the entire wafer. WFPI is achieved by measuring the reflected light intensity from monochromatic uncoherent light at two different planes along the optical path with the same field of view. We show that the lateral resolution in the current system is $24 mumathrm{m}$ but can be pushed to less than $5 mumathrm{m}$ by simply adding more pixels to the image sensor, and that the amplitude resolution limit is 0.3nm. Three 2-inch wafers were measured, and the roughness was revealed by applying a double Gaussian high pass filter to the global topography data.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124713751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advanced Fan Out Wafer Level Package Development for Small form Factor and High-Performance Microcontroller Applications","authors":"G. Sharma, N. Lakhera, Mollie Benson, A. Mawer","doi":"10.23919/IWLPC.2019.8914130","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914130","url":null,"abstract":"Over the last few years fan out wafer level packages (FOWLP) have gained significant traction and industry acceptance in product applications that have small form factor requirements. There are different FOWLP flavors that are in high volume production. High density FOWLP that are used for mobile phone application processors have silicon-package integrated process flow with multiple metal layer interconnects. Conventional FOWLP are limited to single or two metal layer interconnects that are used for RF, Wi-Fi, Codec, PMIC, automotive radar applications. In this study a package was evaluated that uses conventional FOWLP process flow with multiple metal layer interconnect for microcontroller (MCU) applications. Extensive front end-back end process Failure Modes and Effects Analysis (FMEA) and optimization were employed to achieve good assembly process quality, manufacturing performance and reliability for the advanced silicon product. The die pre-assembly process of wafer grind, laser groove, and mechanical saw was developed to meet different in line process quality specs related to laser groove depth and profile, no metal debris in scribe line, top side, back side, side wall chipping. Design of Experiment (DOE) legs including different package interconnect layer stack ups, dielectric materials, and solder alloys were evaluated to achieve optimum bill of material combinations that passed JEDEC standards for product reliability qualification. The conditions tested included: Highly Accelerated Test (110°C/85%/3.3V, 528 hours), High Temperature Storage Life (150°C, 2000 hours), Application Level Temperature Cycling ((−40 °C to 125 °C, 600 cycles), Board Level Temp Cycling (−40 °C to 125 °C, 500 cycles) and Board Level Drop Test (1500g/0.5ms, 30 drops). Optimum choice of solder alloy and package redistribution layer stack up led to excellent reliability performance and qualification for all levels of interconnects (silicon-package-board) and successful chip package integration.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129636968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability and Performance of Wafer Level Fan Out Package for Automotive Radar","authors":"W. Hartner, M. Fink, G. Haubner, C. Geissler, J. Lodermeyer, M. Niessner, F. Arcioni, M. Wojnowski","doi":"10.23919/IWLPC.2019.8914100","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914100","url":null,"abstract":"Embedded wafer level ball grid array (eWLB) or FO-WLP (Fan-out wafer-level packaging) is investigated as a package for MMICs (Monolithic Microwave Integrated Circuit) for automotive radar applications in the 77GHz range. Special focus is put on the thermo-mechanical performance to achieve automotive quality targets. The typical fatigue modes “solder ball fatigue” and “copper fatigue”, evolving during thermo-mechanical stress like cycling on board will be discussed. Simulation as well as experimental preparation results for typical fatigue levels are given. In addition, several influencing parameters are listed and rated regarding their effectiveness. The theoretical framework why solder ball fatigue is the only failure mode causing electrical failure is provided. The impact of different thermo-mechanically driven fatigue modes is discussed. The two important parameters to be considered for the functionality of the Radar system are RF (Radio Frequency) and thermal performance. For elaborating the RF performance with present fatigue modes, the phase shift between different channels and pads is analyzed by full-wave EM (Electromagnetic) simulation. It is found that for fatigue levels up to 90% the phase shift stays below specification for single fatigue modes and may approach specification only for an unlikely combination of all 90% fatigue modes. For assessing the thermal performance with present fatigue modes, thermal simulation as well as thermal measurements are used. Assuming 50% degradation in average for all thermal balls, an increase in RTH of up to about 30% is seen. On average for all thermal measurements, the deviation between measurement and simulation is within ±1°C.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121389016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advanced Low-Loss and High-Density Photosensitive Dielectric Material for RF/Millimeter-Wave Applications","authors":"Hirokazu Ito, Kimiyuki Kanno, A. Watanabe, Ryota Tsuyuki, Ryoji Tatara, Markondeya Raj, R. Tummala","doi":"10.23919/IWLPC.2019.8914136","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914136","url":null,"abstract":"Electrically low-loss and high-density interconnection between components in a package have been one of the most critical metrics for next-generation 5G millimeterwave packages. This paper describes an innovative low-loss photosensitive dielectric material, which enables sub-$10 mu mathrm{m}$ photo-patterning and shows low dissipation factor, known as Df. Dielectric properties providing low-loss interconnects were characterized by ring-resonator method. The results showed a dielectric constant (Dk) of 2.8 and a dissipation factor (Df) of less than 0.005 up to 40 GHz. This material is also designed to have a comparatively low curing temperature of 200°C, high elongation >50%, and high adhesion, and low surface roughness. This paper also presents the demonstration of low-loss and high-density signal routings using dual damascene process with the material. The innovative photosensitive dielectric material, reported in this paper, is a promising candidate to enable high-performance, high-density fan-out and interposers for RF and 5G mm-wave applications.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126431735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Leveraging the Best of Package and IC Design for System Enablement","authors":"Bill Acito","doi":"10.23919/IWLPC.2019.8914109","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914109","url":null,"abstract":"We find ourselves firmly in the middle of two different design domains, or at least at a point between two new design domains we were not expecting. Where once package design capabilities and flows were derived from PCB design, we find ourselves squarely between IC design and traditional package design. As SoCs (System-on-Chips) have lost favor as the primary system design enablement vehicle, dimensions have shrunk, system designers focus on de-aggregating their chips to their logical subcomponents manufactured in optimal materials and nodes, we find system designers in a new “middle point”, leveraging the best of IC Package and IC design. Package designers now find themselves in the forefront of system-level design and implementation. Once “system design” was done at the SoC silicon level; packaging is now, arguably, the design domain that enables advanced system design. Designers have many different flows and capabilities at their disposal; based on the interconnect dimensions and the materials available, leveraging the capabilities of what has classically been IC design in advanced packaging is becoming more and more prevalent. Package designers are leveraging IC design flows, manufacturing checks and sign off mechanisms to design the next generation of systems. Silicon-based interconnect at silicon process dimensions has become one more vehicle at the disposal of the advanced package designer. Designers can leverage classic flows and design capability available in the IC design space along with their existing package design capabilities. Being able to drive these flows with tools that can work together, as well as additional tools that can act as the system planner or connectivity manager across these domains gives the designer a definite advantage. Designers who are looking for the next generation of EDA tools to support these design challenges will find themselves working with tools available from both the package and IC design space. We propose that users looking to complete these advanced designs will need to leverage capabilities from both design domains, and complete the design using the best tools in each category. Likewise, users may need a single point of entry and design capture at the system level, as well as the capability to manage the overall connectivity across the entire hierarchy of the design. Flows based on these tools can be created to enable and optimize complex designs and meet physical, signal integrity, cost and performance requirements. This paper will the discus the challenges and requirements for working in the space in between these classic design domains, and how they these capabilities can enable advanced package design going forward.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132590040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"System for Measuring Three-Dimensional Micro-Structure Based on Phase Shifting Fringe Projection","authors":"C. Cho, Y. Ku, Po‐Yi Chang, Han-Wen Lee, C. Lo, Yi-Chang Chen","doi":"10.23919/IWLPC.2019.8914147","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914147","url":null,"abstract":"We have developed a telecentric three dimensional measurement system based on fringe projection techniques to measure the absolute phase corresponding to the three dimensional shape of micro structure profile, like micro bumps, pillars and solder bumps etc. Fringe projecting module with adjustable fringe density and projecting angles are designed to flexibly and accurately introduce the phase shifting algorithm. In tradition, all of the fringe projection techniques are used by two ways, which one is the tri-linear camera obtained three of fringe images by the separate line camera, and the other one is the three fringes image taken and processed through area camera one by one to measure three dimensional profiles. The advantage of the former can provide for high speed scanning phase measuring of an object, but it can't measure mirror like sample, like wafer bumps, because of the hardware limited. And the latter can measure mirror like sample but the technology need to be changed the phase module of the light source lead to the measurement speed to be slow. In this paper, we use the area camera to acquire three of fringe images with 120° phase shifting simultaneously by the pixels in each rows without changing the phase module of the light source are sufficient to reconstruct a 3D model. By using this technique, we can further improve the measuring speed of the structure light system, and the system will be more resistant to fast moving objects. The measurement accuracy for the height of the micro bumps range of $5-2000 mumathrm{m}$ is verified as less than $1 mumathrm{m}$.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128484243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}