2019 International Wafer Level Packaging Conference (IWLPC)最新文献_第5页

A Unique and Robust Technique to Eliminate Warpage for FOWLP and FOPLP During the Termal Debonding Process 一种独特的消除FOWLP和FOPLP在终端脱粘过程中翘曲的鲁棒技术

2019 International Wafer Level Packaging Conference (IWLPC) Pub Date : 2019-10-01 DOI: 10.23919/IWLPC.2019.8914129

Debbie Claire Sanchez, Klemens Reitinger, Sophia Oldeide, Kang Zhao, Wenxuan Song, Ibrahim Khwaja

引用次数: 4

Latest Technologies of Epoxy Molding Compound (EMC) for FO-WLP FO-WLP环氧成型复合材料(EMC)的最新技术

2019 International Wafer Level Packaging Conference (IWLPC) Pub Date : 2019-10-01 DOI: 10.23919/IWLPC.2019.8914120

Takeshi Mori

引用次数: 3

Non-Destructive 3D Characterization of Application Processor Panel Level Package Used in Galaxy Smartwatch Galaxy智能手表应用处理器面板级封装的无损3D表征

2019 International Wafer Level Packaging Conference (IWLPC) Pub Date : 2019-10-01 DOI: 10.23919/IWLPC.2019.8914126

T. Gregorich, Masako Terada, C. Hartfield, A. Gu, Jan Vardaman

{"title":"Non-Destructive 3D Characterization of Application Processor Panel Level Package Used in Galaxy Smartwatch","authors":"T. Gregorich, Masako Terada, C. Hartfield, A. Gu, Jan Vardaman","doi":"10.23919/IWLPC.2019.8914126","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914126","url":null,"abstract":"Modern wearable electronic devices have been available for nearly 35 years. However, in the past few years significant improvements have been made in the size, weight and usability of these products. While silicon scaling has contributed to achievement of these performance levels, newly developed IC packages are also key enabling technologies for these products. Wafer level package (WLP), panel level package (PLP) and package on package (POP) are technologies that are becoming increasingly popular for wearable and mobile products because they allow chips to be assembled into smaller packages, placed nearer to each other and joined with superior electrical interconnect systems. The Application Processor Module in the Galaxy Watch uses a novel PLP-POP design which meets both the performance requirements as well as the size requirements of Samsung's latest smartwatch. Previously, characterization of chips in IC packages with buried interconnects was done using traditional methodologies such as cross-section and optical microscopy. These techniques, however, can be slow and are prone to missing evidence that was not exposed by the cross-section cuts. New characterization methodologies such as X-ray inspection and measurement provide a richer, more complete assessment of these advanced designs. In this paper the Application Processor Module in the 2019 Galaxy Watch was characterized using a new type of non-destructive package inspection and measurement technology, known as X-ray Microscopy. Using this methodology, we were able to extract data and make conclusions on the results of the manufacturing processes, measure critical dimensions and assess key characteristics of the product, all done non-destructively with the Galaxy Watch PCB and Application Processor Module intact. Additional higher-resolution measurements could be made if the module was removed from the PCB and the shields.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122488535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Glass Solutions for Wafer Level Packaging 晶圆级封装的玻璃解决方案

2019 International Wafer Level Packaging Conference (IWLPC) Pub Date : 2019-10-01 DOI: 10.23919/IWLPC.2019.8914119

A. Shorey, S. Nelson, D. Levy, P. Ballentine

{"title":"Glass Solutions for Wafer Level Packaging","authors":"A. Shorey, S. Nelson, D. Levy, P. Ballentine","doi":"10.23919/IWLPC.2019.8914119","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914119","url":null,"abstract":"Glass substrates with fine-pitch through-glass via (TGV) technology give an attractive approach to wafer level integration. Glass can be made in very thin sheets (<100 um thick) which aids in integration and eliminates the need for back-grinding operations. Electrical and physical properties of glass have many attractive attributes such as the ability to provide low loss performance, adjust thermal expansion properties and low roughness with excellent flatness to achieve fine L/S. Furthermore, glass can be fabricated in panel format to reduce manufacturing costs. The biggest challenge to adopting glass as a packaging substrate has been the existence of gaps in the supply chain, caused primarily by the difficulty in handling large, thin glass substrates using standard automation and processing equipment. This paper presents a temporary bonding technology that allows the thin glass substrates to be processed in a semiconductor fab environment without the need to modify existing equipment. The approach utilizes a thin inorganic adhesion layer to bond a thin glass wafer to a silicon or glass handle wafer (Si handle wafer is the primary approach). The thin glass substrate, which may contain through-glass vias (TGVs), is then processed through downstream steps such as via fill, CMP, RDL/passive deposition, lithography and bumping. The bond is stable (remains temporary and without outgassing) to over 400°C. Utilizing a Si handle wafer allows the thin glass to be processed leveraging existing processes, with only a mechanical de-bond to yield finished substrates. An attractive benefit to this approach is that it lends itself to creating wafer-level multi-layer stacks. We will provide an overview of the technology and examples of the demonstrated process.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123197008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

System Co-Design Inclusive of Connectivity for 3DIC and Wafer-Level Packaging 包括3DIC和晶圆级封装连接的系统协同设计

2019 International Wafer Level Packaging Conference (IWLPC) Pub Date : 2019-10-01 DOI: 10.23919/IWLPC.2019.8913984

TV Narayanan

{"title":"System Co-Design Inclusive of Connectivity for 3DIC and Wafer-Level Packaging","authors":"TV Narayanan","doi":"10.23919/IWLPC.2019.8913984","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8913984","url":null,"abstract":"With the drive towards adding more functionality on a system and the era of artificial intelligence and IoT in play, the semiconductor industry has responded by moving away from the Moore's law approach of shrinking the chip and instead focusing on 3D integration of dies and/or packages. While by itself this poses significant challenges in the manufacturing and testing of these new architectures, there is also a need to address the issues this creates for the design flow itself. The key difference in design flow is the increasing number of iterations, not only of designs, but also the combination of designs. One die may be used across multiple packages or PCBs. This necessitates the need to create flows which are cognizant of variations. Added to this is the complexity of having to tackle new architectures like fan out wafer-level packaging or 3D ICs. The classical methodology of passing the design information from the between chip/package and package/PCB teams will be much too restrictive, costly and potentially the key to faster time-to-market product. This paper explores the solution to this the complex system connectivity optimization challenge and further demonstrates a way to track and verify connection changes throughout the design process.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114054836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1