2019 International Wafer Level Packaging Conference (IWLPC)最新文献

{"title":"Highly Integrated SIP for Mobile Device","authors":"Junghwa Kim, Heeseok Lee, Heejung Choi, James Jeong, Yunhyeok Im","doi":"10.23919/IWLPC.2019.8914111","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914111","url":null,"abstract":"In mobile application, to integrate the required functions in the limited area is one of the key points of the success of the products. The industries have studied the way of integration method by adopting system on chip or system in package approach. With the conventional approach using laminate substrate, there had been the limit of integration due to its limited pattern capability and larger keep out zone for underfill. It's known that fan-out package is one of the effective solutions to make the compact system. One of the most important factors is to achieve fine joint pitch to make the system within Package on Package format. In this study, the system integration by using advanced packaging technology like fan-out PLP will be provided. One of wearable devices had been selected to see the effect of integration. In conventional approach, the devices had been placed on main PCB, respectively. To make the area compact, some of PKG types were selected and compared. Finally, we had found the most effective package format for fine form factor.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122263652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermomechanical Characterization of Polymer Thin Films. Application for the Conception and the Manufacturing of a 3D Interposer","authors":"L. Vignoud, Nicolas Assigbe, C. Morin, J. Dechamp, Lucile Roulet, G. Parry, R. Estevez","doi":"10.23919/IWLPC.2019.8914090","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914090","url":null,"abstract":"Over the past few years, polymers have appeared almost everywhere in microelectronics. Their conditions of processing and the high variability of their mechanical properties require the use of materials such as glue, passive layer, underfill etc. The mechanical behavior of polymers is characterized by viscoelasticity and so a dependence of the temperature and the frequency of loading. As a result, when we consider the mechanical properties of devices containing polymers, we need to consider the thermo-evolution of the Young modulus (E) and the CTE ($alpha$) as their properties are not constants. For measuring the evolution of thin films thermomechanical properties, we used a metrology tool called kSAMOS ThermalScan. k-Space Associates Inc developed this thin-film metrology solution composed of an optical module producing and measuring an array of parallel laser beams, a high resolution scanning stage, a rapid thermal processing (RTP) chamber and several accessorial gas control modules. In this work we will present the measurement capabilities of this tool and the results obtained in the case of evolving materials. We will integrate the thermomechanical properties of films in our analytical model for the prediction of the stress distribution “$text{Sigmap}varepsilontext{ps}$”. By means of this model, we consider the whole thermal history of the multilayer system as well as processing conditions which are taken into account for each layer. For the manufacturing of a 3D Silicon Interposer, designers need to stack integrated circuits and connect them vertically. To obtain a functional devise, stresses and strains must be controlled during all the steps of manufacturing. For example, the cutting and the thinning of the substrate increases the strain leading to possible connection problems and consequently difficulties with alignment during assemblies made at high temperatures. Coupling experimental measurements and analytical model allows us to control the bow and the stress distribution in this multi-layered structure.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121219062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Producing Vias in Photosensitive Polyimide Passivation Layers for Fan Out PLP Through the Integration of an Advanced Lithography System with a Novel Nozzle-Less Spray Coating Technology","authors":"S. Erickson, C. Ayala, Sanjay Malik","doi":"10.23919/IWLPC.2019.8913919","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8913919","url":null,"abstract":"As demand for ever more powerful personal handheld devices and advanced computing systems continues to grow, front-end manufacturers have pushed Moore's Law to the limit and integrated more functionality into their chips while at the same time reducing their physical footprint. Modern chips now contain more I/O channels in smaller areas than ever before. The interconnection of these devices has become more challenging along with competing demands to reduce costs and increase throughput. New methods are required to meet these challenges. There are inherent topographical challenges associated with the growth of 2.5D and 3D packaging where chips are placed and interconnected horizontally and vertically. The industry's drive for cost reduction is building momentum toward more efficient and cost effective methods for creating the multi-layer high density interconnects. One critical area of interest is the formation of the passivation layer that enables connections between layers. Polyimides must be applied in a uniform layer to ensure that the inter-layer connections can properly be formed. This paper demonstrates the feasibility of a revolutionary technique in the form of nozzle-less ultrasonic spray technology in conjunction with a next generation advanced packaging lithographic system for the creation of high-density vias. Performance parameters including polyimide thickness uniformity, and CDU will be compared and analyzed for this approach against other liquid film application methods. Results from the examination of the efficacy, cost reduction potential of this novel method for high-volume manufacturing will be presented.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122590213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultra-Low Warpage and Excellent Filling Ability Liquid MUF for Advanced Fan-Out Wafer Level Package","authors":"Yohei Nishimura, Atsushi Kisanuki, Ohashi Hikaru, Ishigaki Masaki, Naoki Kanagawa","doi":"10.23919/IWLPC.2019.8913990","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8913990","url":null,"abstract":"In recent years, the demands for higher speed and smaller and thinner semiconductor devices are increasing, and the demand for fan-out wafer level package (FOWLP) technology is expected to grow in the future [1]–[3]. Resin formulation for FOWLP is very important because the properties of the epoxy molding compound (EMC) greatly affect the performance of the devices. To meet the demand for higher performance devices, EMC development will be required to have improve functions such as low loss characteristics and high thermal performance [4]–[6]. Meanwhile, the New package designs tend to have large I/O counts to support higher functionality, even while miniaturization of the interconnect pitch accelerates. Additionally, there will be a demand for fan-out Wafer Level System in Package (SiP) to integrate multiple ICs into one package [7]. Along with the evolution of packages, reduction of warpage and filling the narrow gap under IC chip and between IC chips without voids is becoming more difficult. Liquid capillary flow underfill (CUF) has traditionally been used to fill these narrow spaces. After the dispensing process, the CUF is cured and molded with EMC. However, this two-step method is less than optimal in terms of productivity [8]. We have developed liquid Molded Underfill (MUF) exhibiting ultra-low warpage and excellent filling ability for high density FOWLP by using the following approaches: 1)Optimizing the resin viscosity and filler particle size and distribution to improve filling ability, 2)Modifying the coefficient of thermal expansion, modulus and curing shrinkage of the material to improve warpage performance, 3)Evaluate the influence of curing conditions on resin shrinkage rate and warpage. This study confirmed that low package warpage was achieved and narrow gap filling (below $10mumathrm{m}$) is possible using the developmental liquid MUF. These materials were also evaluated on a CoW test vehicle to verify their viability.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"261 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134174724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Innovative Plating for Heterogeneous Integration","authors":"Richard Boulanger, J. Hander, Robert Moon","doi":"10.23919/IWLPC.2019.8913849","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8913849","url":null,"abstract":"Panel plating requirements are much more demanding as more applications migrate from silicon to panel assembly such as Panel Level Fan Out (PLFO) to leverage the large sizes of the panels. More recently, Heterogeneous Integration (HI) like Intel's Embedded Bridge (EMIB) or various other embedded die concepts are also pushing the boundary for typical panel structures. Line widths and spaces less than 10 Microns, thickness uniformity better than 10%, via topology free of voids and the same height as the redistribution lines are critical. Traditional Panel plating tools are mostly for bulk processing and are not designed to handle these additional requirements. A new tool was required to overcome these challenges. An electroplating process with a single panel per reservoir approach is used. An overhead transporter brings the individual panels that have been pre-loaded in a rigid panel holder designed to handle large currents as well as reduce the warpage to a series of plating reservoirs as well as pre and post processing steps with the tool. The first process is to reduce voiding by removing all air in a vacuum chamber and then inserting degassed water in the same chamber to “prewet’ the panel. Panels are then typically immersed in an acid bath known as an activation step before processing in the plating cells. The plating cells are customized for each metal layer but often include a fine alignment feature, a current uniformity optimizing shield, multiple anode channels for dynamic uniformity along with an agitation mechanism to produce a uniform thin boundary layer at the panel surface. This whole mechanism needs to be very close to the panel, yet still allow some warpage typically associated with panel manufacturing. This paper will demonstrate that it is possible to achieve better line density, bump thickness uniformity and void free vias to allow semiconductor like assembly for Heterogeneous Integration on a standard Printed Circuit Board (PCB) instead of more expensive semi additive processes or silicon interposers.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130600220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Chip to Wafer Hybrid Bonding with Cu Interconnect: High Volume Manufacturing Process Compatibility Study","authors":"Guilian Gao, P. Mrozek, Thomas Workman, L. Mirkarimi, G. Fountain, J. Theil, Gabe Guevara, C. Uzoh, Bongsub Lee, Ping Liu","doi":"10.23919/IWLPC.2019.8913877","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8913877","url":null,"abstract":"Solder reflow technology is volume manufacturing ready to an interconnect pitch of about 60um for two main reasons. Solder has the ability to compensate for height differences among the interconnects on a die or package through the melting and re-solidification process. The second reason is that pick-and-place tools combined with mass reflow process offer an extremely high throughput and low cost process. Unfortunately, this technology appears to be limited to a minimum pitch of $40 mu mathrm{m}$. Therefore, the industry is searching for a solid state bonding technology to enable further pitch scaling. The candidate technology should have the following key attributes: 1) a mechanism to precisely control the metal height variation to prevent open joints, 2) high assembly throughput; 3) low temperature for certain applications; and 4) a pathway to future generations of pitch scaling. DBI® Ultra is a die to wafer (D2W) Direct Bond Interconnect (DBI®) technology that utilizes D2W low temperature hybrid bonding to achieve all of the attributes listed above. It offers precise Cu height variation control through the chemical mechanical polishing (CMP) process. With an extremely efficient pick and place process for assembly, it has a throughput comparable to the solder flip chip reflow process. A spontaneous dielectric-to-dielectric bond at room temperature with a metal-to-metal connection (usually Cu-to-Cu bond) by a low temperature batch annealing process (150–300°C) is attractive for heterogeneous integration. Ultimately, it can scale to a sub-micron pitch. In the past two years, significant progress has been made in the DBI Ultra technology. A bonding process with high volume production throughput has been demonstrated with electrical test yield above 90% with a daisy chain structure that covers 50 mm2 of bonding area. The bonded parts also showed superior reliability performance in temperature cycling, high temperature storage and autoclave testing. This paper demonstrates the low temperature anneal capability of the technology and presents the detailed comparative analysis of the technology against the competing solid Cu-to-Cu thermal compression bonding (Cu-Cu TCB) process.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132092889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Foplp Lithography Solutions to Overcome Die Placement Error, Predict Yield, Increase Throughput and Reduce Cost","authors":"K. Best, John F. Chang, Mike Marshall, Jian Lu","doi":"10.23919/IWLPC.2019.8913865","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8913865","url":null,"abstract":"The Internet of Things (IOT), mobile devices, memory and automotive applications are major market drivers. These drivers require high performance, low cost, increased functionality and reliability (especially for automotive), 2.5D and 3D packaging solutions. Fan out panel level packaging (FOPLP) is one of the technologies that has the potential to meet these packaging requirements. FOPLP processes require the reconstitution of dies on a substrate, which are displaced from their nominal grid location during the epoxy molding compound process. This fan out technology delivers more space for redistributed I/O connections, providing increased flexibility for homogeneous and heterogeneous integration. Moreover, the final package size can be increased since the panel format supports more packages per substrate than 300mm wafers. Although FOPLP processing has many advantages, it also faces significant challenges. One critical challenge is the reconstituted die placement error, which occurs during the reconstitution and molding process. These placement errors are amplified with the larger panel format when compared to reconstituted wafers, and errors of $50mumathrm{m}$ or more are not unusual. In order to guarantee acceptable yield, these errors must be corrected during the lithography process using site by site corrections. Conducting metrology and site by site exposures on the lithography system is very time consuming. Substrate alignment and error correction are traditionally calculated using global alignment, but this correction does not accommodate the non-linear die placement errors. It has become clear that only site corrections can deliver the overlay required to maintain good yield. Typically, this approach has a huge impact on throughput and would increase the cost of FOPLP process making it impractical. In this paper we demonstrate a revolutionary FOPLP lithography solution for the die placement error challenge. We describe the use of an external metrology tool to capture die placement error data from a panel, and a “feed forward” solution to optimize stepper, site by site, X, Y and rotation offsets, during exposure. We also show how visualization of the metrology data provides the user with the ability to characterize upstream and downstream processes together with a unique yield predication capability. This solution significantly increases stepper throughput, reducing cost and increasing productivity whilst ensuring high yield.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128328764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Density Flex and Thin Chip Embedding Technology for Polymeric Interposer and Sensor Packaging Applications","authors":"K. Zoschke, P. Mackowiak, H. Ngo, C. Tschoban, C. Fritsche, I. Ndip, Kevin Kröhnert, K. Lang","doi":"10.23919/IWLPC.2019.8914091","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914091","url":null,"abstract":"The paper introduces a fabrication technology for high-density flex circuits. The technology is based on wafer level packaging processes such as electro chemical metal deposition as well as deposition and structuring of polymeric interlayer dielectrics to create multi-layer wiring at rigid carrier wafers. The flex circuits are created subsequently by laser assisted detach of the multi-layer stack from the carrier wafers, which can be performed at full area or partially to create flex or rigid-flex configurations. The base technology enables line pitches down to $24 mumathrm{m}$ and staggered via configurations in a stack-up of up to three internal routing layers as well as front and back side contacts with minimum pitch of $55 mu mathrm{m}$. Depending on the layer stack-up total flex thicknesses between 20 and $50 mu mathrm{m}$ are possible. The advanced technology enables line pitches of $14 mumathrm{m}$ and stacked via configurations with minimum via diameters of $10 mumathrm{m}$ in $10 mumathrm{m}$ thick polymer layers and a minimum pitch of the front and back side IOs of $27 mu mathrm{m}$. A further extension of the base technology allows the embedding of ultra-thin ICs into the multi-layer stack-up. The dices are $20 mumathrm{m}$ thin and placed in face-up configuration onto a die bonding adhesive. The thin ICs are then over coated with the next polymer layer and thus embedded into the thin film multilayer stack. As one demonstrator an acceleration and vibration sensor system was build. The demonstrator includes 2 ultra-thin sensor chips which are embedded in a $50 mu mathrm{m}$ thick RDL layer stack on a rigid carrier. The vibration detection is enabled by a stress sensor chip, which is embedded in a partially freestanding only $50 mumathrm{m}$ thin flex layer. As second demonstrator a 24 GHz radar sensor was build. The sensor includes 2 embedded ultra-thin 24 GHz transceiver ICs.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123165222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advanced RF Packaging Technology Trends, from WLP and 3D Integration to 5G and Mmwave Applications","authors":"Stéphane Elisabeth","doi":"10.23919/IWLPC.2019.8914089","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914089","url":null,"abstract":"In the last few years, radio frequency (RF) applications have driven the advanced electronics packaging market to encompass different sectors. With products such as Automotive Radar, High-End Smartphones or WiGig devices, the RF packaging market is expected to grow in every sector. Wafer-level packaging (WLP), 3D through-silicon vias (TSVs), SiPs (Systems-in-Packages), and electromagnetic interference (EMI) shielding are key enablers for heterogeneous integration in segments where RF devices require small form factors, high speed operation and a high degree of isolation. Also, cost efficiency is critical. Based on images extracted from physical analyses of several RF devices, we will demonstrate the present power of RF packaging solutions for manufacturers such as Qualcomm, Broadcom, and Skyworks, from the manufacturing cost to the functional integration. We will extract some clues for future fifth generation (5G) and millimeter wave (mmWave) applications. We will also present how these companies manage to provide highly integrated SiPs featuring several advanced packaging technologies cost-effectively. Finally, moving forward in 5G and mmWave applications, SiPs will get more complex to maintain high performance levels, with innovations like integrated EMI shielding and integrated passive devices. We will therefore introduce some key features, like advanced substrate technologies. These are also next generation technologies for 5G and mmWave systems.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124150727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Heterogeneous Integration Solutions for HPC Application by Using FO-MCM Chip Last Platform","authors":"P.J. Su, George Pan, Nistec Chang, Yu-Po Wang","doi":"10.23919/IWLPC.2019.8914123","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914123","url":null,"abstract":"For years high performance computing (HPC) products have been integrating more and more functions in the IC. Large die size with high density transistor is still the trend for IC product design, especially networking and CPU product. As Moore's law nears its physical limits, split die and heterogeneous integration in package are the effective solution to increase gross die and wafer yield for cost saving. In order to fulfil electronical performance, line width/ space small than 5/5um is necessary for die to die high density IO interconnection. Currently, 2.5DIC package is one of the mature solutions for fine line interconnection in the industry. Besides, fan-out multi-chip module (FO-MCM) is an alternative technology with low cost benefit that uses redistribution layer (RDL) instead of silicon interposer. For different segment of applications, FO-MCM chip last and chip first platform are widely used in industry. Chip last process has lower thermal budget on die, no die loss due to know good RDL and shorter cycle time advantages, which is ideal for applications requires multi dies as well as fine RDL interconnections. However, it still has the warpage control challenge with bump non-wetting/ bridge concern, due to the mold grinding process on FO module with complex composition (chip with ubump, underfill and compound). In this study, we will address the package warpage performance and the relationship of FO final thickness by FO-MCM chip last process. Finally, we will demonstrated three layer RDL structure and minimum line width/ space down to 2/2um. Package level reliability qualification is also finished with temperature cycle test (TCT), unbiased highly accelerated stress test (uHAST) and high temperature storage life (HTSL) conditions.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132263965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}