Producing Vias in Photosensitive Polyimide Passivation Layers for Fan Out PLP Through the Integration of an Advanced Lithography System with a Novel Nozzle-Less Spray Coating Technology

S. Erickson, C. Ayala, Sanjay Malik
{"title":"Producing Vias in Photosensitive Polyimide Passivation Layers for Fan Out PLP Through the Integration of an Advanced Lithography System with a Novel Nozzle-Less Spray Coating Technology","authors":"S. Erickson, C. Ayala, Sanjay Malik","doi":"10.23919/IWLPC.2019.8913919","DOIUrl":null,"url":null,"abstract":"As demand for ever more powerful personal handheld devices and advanced computing systems continues to grow, front-end manufacturers have pushed Moore's Law to the limit and integrated more functionality into their chips while at the same time reducing their physical footprint. Modern chips now contain more I/O channels in smaller areas than ever before. The interconnection of these devices has become more challenging along with competing demands to reduce costs and increase throughput. New methods are required to meet these challenges. There are inherent topographical challenges associated with the growth of 2.5D and 3D packaging where chips are placed and interconnected horizontally and vertically. The industry's drive for cost reduction is building momentum toward more efficient and cost effective methods for creating the multi-layer high density interconnects. One critical area of interest is the formation of the passivation layer that enables connections between layers. Polyimides must be applied in a uniform layer to ensure that the inter-layer connections can properly be formed. This paper demonstrates the feasibility of a revolutionary technique in the form of nozzle-less ultrasonic spray technology in conjunction with a next generation advanced packaging lithographic system for the creation of high-density vias. Performance parameters including polyimide thickness uniformity, and CDU will be compared and analyzed for this approach against other liquid film application methods. Results from the examination of the efficacy, cost reduction potential of this novel method for high-volume manufacturing will be presented.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International Wafer Level Packaging Conference (IWLPC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/IWLPC.2019.8913919","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

As demand for ever more powerful personal handheld devices and advanced computing systems continues to grow, front-end manufacturers have pushed Moore's Law to the limit and integrated more functionality into their chips while at the same time reducing their physical footprint. Modern chips now contain more I/O channels in smaller areas than ever before. The interconnection of these devices has become more challenging along with competing demands to reduce costs and increase throughput. New methods are required to meet these challenges. There are inherent topographical challenges associated with the growth of 2.5D and 3D packaging where chips are placed and interconnected horizontally and vertically. The industry's drive for cost reduction is building momentum toward more efficient and cost effective methods for creating the multi-layer high density interconnects. One critical area of interest is the formation of the passivation layer that enables connections between layers. Polyimides must be applied in a uniform layer to ensure that the inter-layer connections can properly be formed. This paper demonstrates the feasibility of a revolutionary technique in the form of nozzle-less ultrasonic spray technology in conjunction with a next generation advanced packaging lithographic system for the creation of high-density vias. Performance parameters including polyimide thickness uniformity, and CDU will be compared and analyzed for this approach against other liquid film application methods. Results from the examination of the efficacy, cost reduction potential of this novel method for high-volume manufacturing will be presented.
通过集成先进光刻系统和新型无喷嘴喷涂技术,在光敏聚酰亚胺钝化层中生产扇出式PLP的通孔
随着对更强大的个人手持设备和先进计算系统的需求不断增长,前端制造商已经将摩尔定律推向极限,在减少物理足迹的同时将更多功能集成到芯片中。现代芯片现在比以往任何时候都在更小的区域包含更多的I/O通道。随着降低成本和提高吞吐量的竞争需求,这些设备的互连变得更具挑战性。需要新的方法来应对这些挑战。在2.5D和3D封装的发展过程中,存在固有的地形挑战,其中芯片是水平和垂直放置和连接的。业界对降低成本的追求,正在推动采用更高效、更具成本效益的方法来创建多层高密度互连。我们感兴趣的一个关键领域是钝化层的形成,钝化层可以实现层与层之间的连接。聚酰亚胺必须涂在均匀的层中,以确保层间连接能够正确形成。本文展示了一种革命性的无喷嘴超声喷涂技术的可行性,该技术与下一代先进的封装光刻系统相结合,用于创建高密度过孔。将该方法的性能参数包括聚酰亚胺厚度均匀性和CDU与其他液膜应用方法进行比较和分析。对这种新方法的有效性和成本降低潜力的研究结果将用于大批量生产。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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