2019 International Wafer Level Packaging Conference (IWLPC)最新文献

{"title":"Advanced Black Resist Processing and Optimized Lithographic Patterning for Novel Photonic Devices","authors":"B. Matuskova, H. Taguchi, M. Weinhart, R. Holly, M. Brunnbauer, J. Rimböck, T. Zenger, M. Eibelhuber, T. Uhrmann, Y. Taguchi","doi":"10.23919/IWLPC.2019.8914139","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914139","url":null,"abstract":"CMOS image sensors technology is nowadays widely used in various applications due to multiple advantages, such as low cost, low power consumption, on chip functionality, high-speed of operation [1]. The market for CMOS image sensor (CIS) technology is continuously growing, as this technology is key technology in the most of the main electronic megatrends, such as smart automotive, portable & mobile electronics, novel human machine interfaces for AR/ VR devices, 3D sensing or $mu$-displays and advanced healthcare requirements. In order to follow and continue CIS scaling for thinner and smaller devices, an adoption of new processes and materials is required. Mainly improving optical performance as well as imagining characteristics of image sensors, such as higher image resolution, better contrast and desired optical density of the colored resist materials are key aspects of today's development.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129730045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal Laser Seperation with Deep Scribe for Silicon Wafer Dicing","authors":"C. Belgardt","doi":"10.23919/IWLPC.2019.8914142","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914142","url":null,"abstract":"TLS-Dicing (Thermal Laser Separation) is a unique technology for separating wafers into single chips in semiconductor back end processing. TLS-Dicing uses thermally induced mechanical stress to separate brittle semiconductor materials, like silicon (Si) and silicon carbide (SiC) wafers. TLS is a two-step TLS-Dicing method consisting of scribing and cleaving. The scribing is used to create a starting point of the second step – the cleaving step. A continuous wave laser in combination with water spray cooling generates a thermal distribution. This leads to a mechanical stress capable to guide one defined crack along the dicing street which leads to the separation of the material. This work investigates a new scribing method – the Deep Scribe – in detail. While using Deep Scribe a pulsed laser beam of near infrared wavelength is focused with an objective into the silicon. This generates a line of subsurface material modification. By using this scribe technique no particles occur at the surface. Additionally, straightness and the bending strength of separated silicon chips can be improved in comparison with state of the art dicing technologies. In this presentation, we will discuss the latest developments in Deep Scribe TLS with focus on the physical effects of the interaction between laser beam and material, as well the requirements for generation of a Deep Scribe. We will investigate the influence of adjusting parameters such as focus position, duration of laser pulse and laser power, on position and size of the modified area. We will also study the effects of thermal laser separation with Deep Scribe on bending strength of diced chips, a crucial parameter for wafer thinning applications. For comparison, similar wafers were cut with current state-of-the-art mechanical blade dicing.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132028731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Process Development for Flip Chip Bonding with Different Bump Compositions","authors":"S. Massa, David Shahin, I. Wathuthanthri, Annaliese Drechsler, R. Basantkumar","doi":"10.23919/IWLPC.2019.8913986","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8913986","url":null,"abstract":"While developing new processes in the area of microchip electronic packaging, the goal is to increase quality and throughput while lowering cost. In the traditional backend assembly process for mature technologies, the die are singulated, sorted, mounted onto packages, and then wire bonded to the next higher assembly. Flip chip technology restructures the traditional assembly flow by mounting an electronic chip face down to a substrate, eliminating the need for die mount or wire bonding. Apart from process reduction, other advantages include increased I/O density, better thermal dissipation, and better connection performance based on low impedance from a significantly shorter bond length compared to wire bonding. Northrop Grumman's Advanced Technology Lab (ATL) has explored capabilities for assembly using multiple flip chip bump materials including gold, indium, and lead-tin solders. Each of these different material categories required different approaches to yield a proper bond. For example, gold-to-gold thermocompression bonding required a bonding profile with high force and temperature in an ambient air environment, while lead-tin solder requires little to no force, but needs exposure to a flux or other oxidation-eliminating agent. This initial process assessment leads to future studies that will be done to grow the flip chip bonding proficiency. Northrop Grumman is currently exploring throughput enhancement of gold-to-gold thermocompression flip chip bonding. This study is investigating the profile parameters of force, temperature, and dwell time and how they affect the compression and bond strength of the flip chip bonded assembly. The results of this study have already improved the throughput for Northrop Grumman gold thermocompression flip chip bonding, and will also help build the method for flip chip bonding process development for future studies. In the coming year, ATL plans to expand flip chip capability by exploring current applications to enhance the process capability.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115015956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Effect of Cu Target Pad Roughness on the Growth Mode and Void Formation in Electroless Cu Films","authors":"T. Bernhard, S. Zarwell, E. Steinhäuser, S. Kempa, F. Brüning","doi":"10.23919/IWLPC.2019.8914011","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914011","url":null,"abstract":"The electrical reliability of multilayer High Density Interconnection Printed Circuit boards (HDI PCBs) is mainly affected by the thermo-mechanical stability of stacked micro via interconnections. In this regard, a critical failure mode is the stress related crack between the electrolytically filled via and the target pad, commonly known as target pad separation. The junction includes two Cu-Cu-interfaces, one between the target Cu pad and the thin electroless Cu layer and the second between electroless Cu and electrolytic Cu. To ensure a clean and defect-free target pad/electroless Cu interface, elimination of organic residues (after desmear) and melted Cu (from laser drilling) is a prerequisite. Therefore strong etch cleaners, mostly based on sodium persulfate, are used to remove the top $1-2 mu mathrm{m}$ Cu from the target-pad surface. According to the applied type of etch cleaner and etching intensity, a specific target pad roughness remains as the plating base for the subsequent electroless Cu process. In this context, we investigated the impact of the Cu-base roughness on the growth mode of two different electroless Cu baths. Bath A has a cyanide based and bath B a non-cyanide based stabilizer system, both baths are commonly used in the PCB industry. We found that for a Cu-base roughness at about $mathrm{R}_{mathrm{a}}=300 text{nm}$, two growth modes are observed for electroless Cu bath B. One mode is copying the subjacent Cu-substrate morphology, while the other mode forms spherical grains (Cu-nodules) mostly at the exposed sites of the substrate crystals. These Cu-nodules typically have a radius comparable to, or even higher than the plated electroless Cu thickness and are easily detectable via standard SEM. FIB/SEM-microsections through these Cu-nodules have shown a high density of nano-voids at the base of these features. The voids have typical diameters of some ten to hundred nanometers. A further increase of the Cu-base roughness to $mathrm{R}_{mathrm{a}}=1000 text{nm}$ results in a substantially higher nodule density for electroless Cu bath B. The related void formation seems relevant to weaken the overall Cu/Cu/Cu-interconnection in the blind micro via. Interestingly, the tendency to form nodules with increasing Cu-base roughness is widely suppressed for the cyanide based bath A, where sporadically nodules are not formed until a roughness of $mathrm{R}_{mathrm{a}}=1000 text{nm}$ is achieved. To understand the different impacts of the stabilizer systems A and B, the nucleation of nodules during the first stage of electroless Cu growth was investigated: In the first seconds of plating, the agglomeration of nano-sized Cu crystals at the exposed sites of the substrate Cu-grains (peaks and edges of crystals) is observable for bath B, whereas for bath A these surface sites seem efficiently poisoned by the stabilizer system and no Cu-agglomeration takes place. These nano-porous Cu-agglomerations are the nucleation sites of nodules and cau","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134434269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Validating Die Crack Inspection with Topography Based Image Sensor","authors":"W. Han, Mike Marshall, Bryan Selby, Amy Shay","doi":"10.23919/IWLPC.2019.8914148","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914148","url":null,"abstract":"Semiconductor manufacturers are continuously driving efforts to put more computing power and speed into less volume. At the same time, consumers are demanding devices with more functionality that integrate a variety of interconnected circuit types. The result has been an increasing reliance on advanced packaging technologies that use fab-like processes to integrate multiple chips and to provide the increased I/O capability required. The demand for higher performance electronics in smaller packages has led to the development of wafer level packaging (WLP), panel level packaging (PLP) and fan-out level packaging. The need for low cost, smaller packages with high density interconnects for cell phones and wearable devices has been leading the development of advanced packaging. All of these advanced packaging techniques involve stacking multiple chips in vertical directions. In DRAM memory packaging, there are as many as eight dies integrated vertically and the manufacturers are trying to keep the thickness of the die as minimal as possible to keep an overall thin package profile. Backside thinning of fully processed wafers has become a widely used technique in the industry. Typical final wafer thickness in the early 1990s was around $450mu mathrm{m}$ but current wafers are usually thinner than $50mu mathrm{m}$. As the final wafer thickness is getting thinner, they are becoming more fragile and susceptible to cracks and chips. Chipping and cracks can cause near-term yield and long-term reliability problems. If a chip or crack is discovered during the final processes of advanced packaging, the overall final yield will be lower. If it is not discovered, the end device may not be reliable in the real world and fail for the consumer, a more costly consequence. As wafers became thinner, the industry started seeing sidewall cracks, inner cracks and micro cracks starting from the kerf or street area initiated from wafer sawing. These types of cracks can cause air bubbles around the cracks during the molding process in fan-out packaging and eventually lead to mold cracking which can lead to lower yields. It would be very beneficial if these types of cracks are detected early and the affected die removed. However, these types of cracks are happening underneath the die surface and are difficult to see with traditional bright field and dark field illuminations because they are underneath the top surface. This paper describes inspection challenges for cracks underneath the die surface and possible solutions to overcome the challenges.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125106882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Recent Breakthroughs in Tight Pitch Laser Microdrilling for Mems Guide Plates","authors":"A. Ferguson, M. Gaukroger, D. Karnakis, M. Cullimore, R. Geremia, S. Tuohy, E. Pelletier, N. Braz, G. Harris, A. Kearsley, M. Knowles","doi":"10.23919/IWLPC.2019.8913883","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8913883","url":null,"abstract":"Laser drilling of guide plates for Advanced Vertical Probecards has become a key enabling technology over the past several years. Amongst the key drivers is the switch in demand from circular shaped holes, achievable with both mechanical and laser drilling methods, to rectangular holes for MEMs style probes. These rectangular holes can only readily be produced with the use of laser technology. As semiconductor technology and wafer test advances, an additional driver is high density hole drilling, i.e. the ability to place smaller and smaller holes on tighter and tighter pitches, whilst keeping the material between adjacent holes intact. Typically, the 3D shaped profile of laser drilled holes cannot easily be controlled, with so called “entry rounding” and “taper angle” characteristics restricting tighter hole positioning. The challenge is therefore to develop new processes which essentially eliminate both entry rounding and taper to values of virtually zero. After a recent breakthrough this has now been achieved.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129065855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Application of Acoustic Metrology for In-Line Microbump Process Monitoring in Advanced Packaging","authors":"M. Mehendale, M. Alves, R. Mair, J. Dai, P. Mukundhan, R. Hollman, K. Best, M. Kotelyanskii","doi":"10.23919/IWLPC.2019.8914097","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914097","url":null,"abstract":"Solder-based fine pitch microbumps along with through silicon vias (TSV) enable high density interconnects for die-to-die and die-to-wafer stacking for different applications. With reduction in bump dimensions, several challenges arise that need to be addressed. For example, selection of under bump metallization (UBM), solder and barrier between them can determine the consumption of the UBM by solder and transformation to intermetallic compound (IMC), during thermocompression bonding. In this study, we systematically investigate the effectiveness of PULSE™ metrology on microbumps with a range of diameters and a variety of metal stacks. On wafers with a Ti/Cu seed layer, a test pattern of microbump features with diameters down to $20mu mathrm{m}$ was imaged in $50 mu mathrm{m}$ photoresist and plated with a matrix of bi-layer (Cu/Ni), tri-layer (Cu/Ni/SnAg) and multilayer Cu/Ni/Cu/SnAg stacks to form the microbumps. We present results from the study to demonstrate the capability of the technique for in-line measurements of individual layer thickness.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122663658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Processing and Memory Partitioning Enabled by Low Cost Flip-Chip Stacking","authors":"Fabian Hopsch, A. Heinig","doi":"10.23919/IWLPC.2019.8914106","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914106","url":null,"abstract":"This paper presents a partitioning approach for processing and memory units concluding in a low cost flip-chip stacking. Many of nowadays systems comprise at least a processing unit and some memory for storing data. The requirements for rising bandwidth, brings up new types of memory. This is achieved by increasing the clock and/or using broader interfaces. But raising frequency leads to more effort on the communication channel in terms of signal integrity. The packaging approach presented in this paper, results in a very short communication channel between memory and processor and with achieving high-performance while keeping the communication effort low. The requirements for the IO-cells are reduced, because of this short channel, leading to very small interfaces. All together the solution is a low-cost flip-chip stacking in terms of design and packaging costs.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115454227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluation of a Spring Probe Card Solution for 5G WLCSP Applications","authors":"K. Dabrowiecki, T. Gneiting, José Moreira","doi":"10.23919/IWLPC.2019.8913842","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8913842","url":null,"abstract":"The new 5G wireless standard brings several new challenges for many applications, especially for the wafer level chip scale packaging (WLCSP) technology. WLCSP has been a very successful technology for handheld and portable products. To make the right decisions in the early stages of probe card design for the mmWave frequencies wafer test, the electromagnetic (EM) simulation of the probe card performance is inevitable. Critical is an understanding of the dependencies and relationships between the many interacting probe card parts such as probe head, PCB, and coaxial connectors. This paper describes the challenges in wafer testing for 5G applications and presents the author's experience in the implementation of spring probe cards for 5G mmWave frequencies. This paper presents a spring probe card for 5G technology as a low-cost alternative RF wafer test solution and examines 3D EM computer model simulation results.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129901655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Solutions for Advanced Heterogeneous Integrtion and Fan-Out Processes","authors":"Doug Shelton, Ken-ichiro Mori, Y. Goto, Hiromi Suda","doi":"10.23919/IWLPC.2019.8914096","DOIUrl":"https://doi.org/10.23919/IWLPC.2019.8914096","url":null,"abstract":"High-Performance Computing systems can employ leading-edge Heterogeneous Integration (HI) technology including Fan-Out Wafer Level Packaging (FOWLP) and high-density Redistribution Layers (RDL) to maximize system bandwidth and performance. These More-than-Moore strategies are growing in importance and present unique challenges that must be overcome to enable mainstream adoption. FOWLP roadmaps for interconnections between SoC (System on Chip) and DRAM (Dynamic Random Access Memory), split-die FPGA (Field-Programmable Gate Array) and image sensors and SoC are driving RDL scaling and aggressive FOWLP processes are targeting $0.8 mu mathrm{m}$ design rules. High-resolution lithography is required for high-density, fine-RDL applications and the main lithography challenge is to provide a large Depth-of-Focus (DoF) to reliably pattern sub-micron RDL traces across a large exposure field. This paper details an analysis of candidate optical conditions for sub-micron imaging including data demonstrating the DoF performance of an optimized lithography system (stepper). To meet the high-resolution requirements of fine-RDL processes, Canon developed the FPA-5520iV-HR [20iV-HR] i-line stepper that employs a new projection optical system featuring a maximum 0.24 Numerical Aperture (NA) and a 52 x 34 mm field size. We will present data illustrating that 0.24 NA steppers can provide excellent resolution and pattern fidelity throughout each exposure field across the entire wafer. High-density FOWLP wafers can also display extreme die-shift, warpage and topography that must be addressed to enable high-yield and high-productivity processes. Die placement error in FOWLP wafers creates orders of magnitude more alignment error versus traditional silicon wafers and advanced alignment compensation is required to improve overlay matching. Alignment solutions for processing distorted FOWLP wafers include the Grid-PA system that automatically corrects the wafer loading position based on die-grid sampling, and Enhanced Advanced Global Alignment (EAGA) that allows the stepper to measure and compensate for shift, rotation and intra-field magnification errors on a die-by-die basis. FOWLP reconstituted wafers can also experience large warpage that can decrease productivity and DoF and to combat these challenges, our steppers have been designed to handle wafers with over 5 mm of warpage and are also based on a Front-End-Of-the-Line (FEOL) stepper platform that offers die-by-die tilt and focus measurement and compensation to maximize focus accuracy and DoF. This paper provides an analysis of key lithography challenges facing aggressive FOWLP and fine-RDL processes details of stepper technology that helps enable high-density integration in mass-production. We remain committed to enabling innovation through lithography system performance upgrades and development of original options supporting current and future FOWLP and fine-RDL processes.","PeriodicalId":373797,"journal":{"name":"2019 International Wafer Level Packaging Conference (IWLPC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121075193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}