Novel Temporary Bonding and Debonding Solutions Enabling an Ultrahigh Interonnect Density Fo-Wlp Structure Assembly with Quasi-Zero Die Shift

A. Podpod, Andy Miller, G. Beyer, E. Beyne, Alice Guerrero, Xiao Liu, Qi Wu, K. Yess, Kim Arnold, A. Phommahaxay, P. Bex, K. Kennes, J. Bertheau, H. Arumugam, T. Cochet, K. Rebibis, E. Sleeckx
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引用次数: 3

Abstract

Next-generation temporary bonding adhesive material is introduced into imec's high interconnect density flip chip on fan-out wafer-level package (FC FOWLP) concept [1], [2]. After molding on silicon substrates, an ultralow die shift with an average of $< 2\mu \mathrm{m}$ die-to-carrier mismatch and warpage of $< 200\mu \mathrm{m}$ were achieved in a full 300-mm wafer. These values are orders of magnitude improvement over results reported in literature and has major implications on the processing of overmolded substrates. The combination of this low warp and ultralow distortion opens the possibility for fine-pitch RDL combined with a chip-first approach, which was impossible until now. The evolution of warpage and die shift through multiple processing steps will also be discussed in this paper.
新颖的临时键合和去键合解决方案,实现准零模移位的超高互连密度Fo-Wlp结构组件
imec的高互连密度倒装芯片扇出晶圆级封装(FC FOWLP)概念[1],[2]中引入了新一代临时粘合粘合剂材料。在硅基板上成型后,在一个完整的300毫米晶圆上实现了超低模移,平均< 2\mu \mathrm{m}$模与载流子不匹配和翘曲< 200\mu \mathrm{m}$。这些数值比文献中报道的结果有了数量级的改进,并且对复模基材的处理具有重要意义。这种低翘曲和超低失真的结合打开了细间距RDL与芯片优先方法相结合的可能性,这在现在是不可能的。本文还将讨论在多个加工步骤中翘曲和模移的演变。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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