Semiconductor-On-Polymer the Evolution of thin IC Packaging

Abstract

IC packages are getting thinner to facilitate thinner systems. Labels and tags are getting smarter. Electronics are starting to bend, and reliability is in question. Semiconductor-on-Polymer (SoP) Chip Scale Packaging (CSP) is an enabling technology that can reliably integrate packaged ICs in flexible electronics. SoP™ is being used to produce the leading edge of high performance ultra-thin flexible hybrid electronics and sensors today. Chip Scale Packaging (CSP) defines the logical end of IC package scaling in 2D surface area as package area and IC size converge. Scaling thickness is a key metric in further packaging evolution. SoP CSP provides a path to the end of IC package scaling in 3D volume by reducing package thicknesses to less than what is generally regarded as ultra-thin for bare die. The result is feasibility for packaged ICs to be utilized in direct chip attach (DCA) applications. Die thickness is a key contributor to DCA and FC-BGA IC package thickness. SoP replacement of bare die in conventional IC packaging is envisioned to facilitate package thickness reduction and improved reliability for FC-BGA packages, 3D and heterogeneous integration. This presentation introduces SoP technology and describes SoP CSP direct interconnect (DI) assembly that has progressed from 24-pin attachment to System-on-Chip assembly of DI pitch at ≤100um in flexible hybrid electronics. The presentation also shows the technology roadmap for SoP application to IC packaging and how SoP may fit into current IC packaging roadmaps.