2010 11th International Symposium on Quality Electronic Design (ISQED)最新文献_第6页

Ultra low-voltage, rail-to-rail input/output stage Operational Transconductance Amplifier (OTA) with high linearity and its application in a Gm-C filter 高线性度的超低电压轨对轨输入/输出级运算跨导放大器(OTA)及其在Gm-C滤波器中的应用

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450424

F. Rezaei, S. J. Azhari

引用次数: 12

A low power charge-redistribution ADC with reduced capacitor array 一种小电容阵列的低功率电荷再分配ADC

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450404

M. Kandala, R. Sekar, Chenglong Zhang, Haibo Wang

引用次数: 5

Thermal-aware lifetime reliability in multicore systems 多核系统的热感知寿命可靠性

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450548

Shengquan Wang, Jian-Jia Chen

引用次数: 38

Clock buffer polarity assignment considering the effect of delay variations 考虑延迟变化影响的时钟缓冲极性分配

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450398

Minseok Kang, Taewhan Kim

{"title":"Clock buffer polarity assignment considering the effect of delay variations","authors":"Minseok Kang, Taewhan Kim","doi":"10.1109/ISQED.2010.5450398","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450398","url":null,"abstract":"This work addresses the problem of minimizing power/ground noise with an important design parameter, which is the delay variations on the clock tree. Without considering the effect of delay variations on the polarity assignment, the resulting statistical clock skew may lead to a high probability of skew violation, which causes a low yield of design. Given distributions on the delay of each type of buffering elements and the interconnect delay from the clock source to every flip-flop with spatial delay correlations, and the clock skew and yield constraints, we solve the problem of assigning polarity to each sink buffer (i.e., assigning a buffering type) so that the power/ground noise is minimized while satisfying the yield and clock skew constraints. Specifically, we solve the problem in two steps where in step 1, for each pair of sinks a set of feasible combination(s) of polarities to the sinks that do not violate the yield constraint as well as the clock skew constraint is extracted, and in step 2, a stepwise greedy method is applied to determine the polarities to sinks from the feasible sets obtained in step 1 to minimize the power/ground noise. Through experiments with ISCAS89 benchmark circuits, it is shown that our proposed approach is able to improve yield by 6.7% on average even with 4.3% less power and 4.4% less ground noises over the results by the conventional polarity assignment approach which does not consider the delay variations.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130200857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Hellfire: A design framework for critical embedded systems' applications 地狱火:关键嵌入式系统应用的设计框架

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450495

A. Aguiar, S. J. Filho, F. Magalhães, Thiago D. Casagrande, Fabiano Hessel

{"title":"Hellfire: A design framework for critical embedded systems' applications","authors":"A. Aguiar, S. J. Filho, F. Magalhães, Thiago D. Casagrande, Fabiano Hessel","doi":"10.1109/ISQED.2010.5450495","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450495","url":null,"abstract":"Hellfire framework (HellfireFW) presents a design flow for the design of MPSoC based critical embedded systems. Health-care electronics, security equipment and space aircraft are examples of such systems that, besides presenting typical embedded system's constraints, bring new design challenges as their restrictions are even tighter in terms of area, power consumption and high-performance in distributed computing involving real-time processing requirement. In this paper, we present the Hellfire framework, which offers an integrated tool-flow in which design space exploration (DSE), OS customization and static and dynamic application mapping are highly automated. The designer can develop embedded sequential and parallel applications while evaluating how design decisions impact in overall system behavior, in terms of static and dynamic task mapping, performance, deadline miss ratio, communication traffic and energy consumption. Results show that: i) our solution is suitable for hard real-time critical embedded systems, in terms of real-time scheduling and OS overhead; ii) an accurate analysis of critical embedded applications in terms of deadline miss ratio can be done using HellfireFW; iii) designer can better decide which architecture is more suitable for the application; iv) different HW/SW solutions by configuring both the RTOS and the HW platform can be simulated.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129685761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36

New SRAM design using body bias technique for ultra low power applications 采用体偏置技术的新型SRAM设计，适用于超低功耗应用

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450536

F. Moradi, D. Wisland, H. Mahmoodi, Y. Berg, T. Cao

引用次数: 20

Design of a fault-tolerant coarse-grained 设计了一个容错的粗粒度

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450481

Syed M. A. H. Jafri, S. Piestrak, O. Sentieys, S. Pillement

引用次数: 24

A robust and low power dual data rate (DDR) flip-flop using c-elements 一个鲁棒和低功耗双数据速率(DDR)触发器使用c-元素

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450403

Srikanth V. Devarapalli, P. Zarkesh-Ha, S. Suddarth

引用次数: 28

Low power clock gates optimization for clock tree distribution 时钟树分布的低功耗时钟门优化

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450528

Siong Kiong Teng, N. Soin

引用次数: 19

Analysis and modeling of a Low Voltage Triggered SCR ESD protection clamp with the very fast Transmission Line Pulse measurement 具有快速传输线脉冲测量功能的低压触发可控硅ESD保护钳的分析与建模

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450464

Jae-Young Park, Jong-Kyu Song, Chang-Soo Jang, Young-Sang Son, Dae-Woo Kim

引用次数: 3