2010 11th International Symposium on Quality Electronic Design (ISQED)最新文献_第7页

Modeling and analysis of III–V logic FETs for devices and circuits: Sub-22nm technology III–V SRAM cell design 器件和电路的III-V级逻辑场效应管的建模和分析:Sub-22nm技术III-V SRAM单元设计

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450553

Saeroonter Oh, Jeongha Park, S. Wong, H. Wong

引用次数: 1

Accelerating trace computation in post-silicon debug 加速后硅调试中的跟踪计算

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450450

Johnny J. W. Kuan, S. Wilton, Tor M. Aamodt

引用次数: 2

Methodology to ensure circuit robustness and exceptional silicon quality while proliferating designs across process revisions with high productivity 确保电路稳健性和卓越的硅质量的方法，同时在高生产率的过程修订中激增设计

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450532

N. Srimal

引用次数: 0

Slack allocation for yield improvement in NoC-based MPSoCs 基于noc的mpsoc良率改进的松弛分配

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450496

B. Meyer, Adam S. Hartman, D. E. Thomas

引用次数: 4

Real-time dynamic hybrid BiST solution for Very-Low-Cost ATE production testing of A/D converters with controlled DPPM 用于控制DPPM的A/D转换器的低成本ATE生产测试的实时动态混合BiST解决方案

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450520

S. Dasnurkar, J. Abraham

{"title":"Real-time dynamic hybrid BiST solution for Very-Low-Cost ATE production testing of A/D converters with controlled DPPM","authors":"S. Dasnurkar, J. Abraham","doi":"10.1109/ISQED.2010.5450520","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450520","url":null,"abstract":"The ideal goal of semiconductor quality assurance is to provide zero defective parts to the customer. In practice this goal is limited by test quality and test cost due to expensive ATE resources. It is typically not feasible to provide zero Defective Parts per Million (DPPM) for majority of applications due to the high costs of testing involved. Comprehensive functional tests to find all detectable faults typically have large test times resulting in a prohibitive cost. Work has been done in the field of digital testing with patterns where statistical tools are used in order to optimize the test cost and DPPM by real-time analysis. Our goal is to propose an Analog to Digital Converter (ADC) Built in Self Test (BiST) scheme which has compatibility with similar dynamic optimization measures. Multiple variants of Very Low Cost (VLC)- ATE have been developed for digital testing which rely on relaxed timing, power or tester channel requirements to lower hard-ware cost. Systems containing mixed-signal/RF components typically can not be tested on such ATE due to limitations/lack of analog/RF stimulus and measurement modules on VLC-ATE. This paper proposes a hybrid BIST scheme for ADCs to enable full production-quality testing as well as reduced coverage testing with VLC-ATE. We cover on-chip stimulus generation for a fully functional at-speed test as well as for a low-cost-reduced-coverage approach. Results for the BIST scheme are presented along with a discussion on implementation feasibility and merits. A vector based approach for observing ADC outputs is discussed which could be used with this scheme on VLC-ATE.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117266207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Signal probability control for relieving NBTI in SRAM cells 缓解SRAM细胞NBTI的信号概率控制

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450504

Yuji Kunitake, Toshinori Sato, H. Yasuura

引用次数: 28

Die-level leakage power analysis of FinFET circuits considering process variations 考虑工艺变化的FinFET电路的模级泄漏功率分析

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450554

Prateek Mishra, A. Bhoj, N. Jha

{"title":"Die-level leakage power analysis of FinFET circuits considering process variations","authors":"Prateek Mishra, A. Bhoj, N. Jha","doi":"10.1109/ISQED.2010.5450554","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450554","url":null,"abstract":"In the recent past, FinFETs have been touted as promising alternatives to planar CMOS owing to their superior short-channel characteristics. However, due to lithographic constraints, they are likely to suffer from the effects of process variations, which are manifested as large spreads in leakage current and delay in combinational logic circuits. In this work, we model the leakage probability density function (pdf) in shorted-gate (SG), independent-gate (IG)/low-power (LP), and mixed-terminal (MT) FinFET standard logic cells, and examine the leakage tradeoffs in benchmark circuits synthesized using combinations of SG-, LP-, and MT-mode logic cells under the effect of process variations. Using quasi-Monte Carlo mixed-mode device simulations in Sentaurus TCAD, we develop simple macromodels to capture the physical effects influencing the leakage spread in SG- and IG-mode FinFET devices, and extend it to stacked devices in NAND/NOR gates. We also implement a methodology to obtain the overall leakage current distribution for large circuits (synthesized using SG/LP/MT-mode logic cells) using Latin hypercube sampling, considering spatial correlation on a quad-tree based grid. Results indicate that, starting from a 100% SG-mode circuit, the leakage spread/yield point can be improved considerably by suitably introducing LP-mode and MT-mode gates at iso-delay. We also show that increasing the fraction of LP/MT-mode gates (to reduce the mean and variance in leakage) in an SG-mode circuit, by permitting a delay slack, yields diminishing returns. Mixing LP- and MT-mode gates with SG-mode gates appears to be a promising synthesis strategy that can leverage the leakage tradeoffs offered by FinFET standard cells.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"355 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122800726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 38

Power-yield optimization in MPSoC task scheduling under process variation 工艺变化下MPSoC任务调度的功率优化

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450497

M. Momtazpour, E. Sanaei, M. Goudarzi

引用次数: 14

Useful clock skew optimization under a multi-corner multi-mode design framework 有用的时钟偏差优化下的多角多模式设计框架

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450402

Weixiang Shen, Yici Cai, Wei Chen, Yongqiang Lyu, Qiang Zhou, Jiang Hu

引用次数: 18

Analog behavioral modeling flow using statistical learning method 模拟行为建模流程采用统计学习方法

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450479

Hui Li, M. Mansour, Sury Maturi, Li-C. Wang

引用次数: 3