2010 11th International Symposium on Quality Electronic Design (ISQED)最新文献

Analog placement and global routing considering wiring symmetry 考虑布线对称的模拟放置和全局路由

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450510

Yu-Ming Yang, I. Jiang

引用次数: 15

An accurate modeling method utilizing application-specific statistical information and its application to SRAM yield estimation 一种利用特定应用统计信息的精确建模方法及其在SRAM产量估算中的应用

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450411

Hidetoshi Matsuoka, Hiroshi Ikeda, H. Higuchi, Yoshinori Tomita

引用次数: 1

Optimizing power and throughput for m-out-of-n encoded asynchronous circuits 优化m- of-n编码异步电路的功率和吞吐量

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450406

Jun Xu, Ge Zhang, Weiwu Hu

引用次数: 1

Leakage current analysis for intra-chip wireless interconnects 芯片内无线互连的漏电流分析

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450405

A. More, B. Taskin

引用次数: 9

Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks 时钟树网络中泄漏功率优化的合成后睡眠晶体管插入

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450530

H. Homayoun, Shahin Golshan, E. Bozorgzadeh, A. Veidenbaum, F. Kurdahi

{"title":"Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks","authors":"H. Homayoun, Shahin Golshan, E. Bozorgzadeh, A. Veidenbaum, F. Kurdahi","doi":"10.1109/ISQED.2010.5450530","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450530","url":null,"abstract":"Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip power. In this paper, we propose to deploy sleep transistor insertion (STI) in the clock tree in order to reduce leakage power. We characterize the effect of sleep transistor sharing and sizing on clock tree wakeup time, leakage power, and propagation delay. We use these characteristics during leakage power optimization. We present post synthesis sleep transistor insertion (PSSTI), a heuristic clustering algorithm for sleep transistor insertion with the objective of total power minimization in a given clock tree. Sleep transistor sharing and sizing are deployed in order to meet the clock skew and wakeup delay constraints. We explored the potential benefits of STI using a standard industrial VLSI-CAD flow including sleep-transistor insertion and routing after clock synthesis and place-and-route of the benchmark circuits. Our results show that clock tree leakage power is reduced by 19%–32% depending on the topology of the synthesized clock tree.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"310 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122728328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Clock buffer polarity assignment considering capacitive load 考虑容性负载的时钟缓冲极性分配

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450493

Jianchao Lu, B. Taskin

引用次数: 15

Robust importance sampling for efficient SRAM yield analysis 有效SRAM成品率分析的鲁棒重要抽样

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450410

Takanori Date, Shiho Hagiwara, K. Masu, Takashi Sato

引用次数: 21

Skew analysis and bounded skew constraint methodology for rotary clocking technology 旋转时钟技术的偏差分析和有界偏差约束方法

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450544

V. Honkote, B. Taskin

引用次数: 3

Multi-programming environment for structure under pads (SUP) and via arrays pattern recognition automated classification system 多编程环境下结构垫(SUP)和通过阵列模式识别的自动分类系统

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450519

S. Yusof, Lau Meng Tee

引用次数: 0

Synthesis and formal verification of on-chip protocol transducers through decomposed specification 通过分解规范实现片上协议传感器的合成与形式化验证

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450526

M. Fujita, H. Tanida, Fei Gao, Tasuku Nishihara, Takeshi Matsumoto

{"title":"Synthesis and formal verification of on-chip protocol transducers through decomposed specification","authors":"M. Fujita, H. Tanida, Fei Gao, Tasuku Nishihara, Takeshi Matsumoto","doi":"10.1109/ISQED.2010.5450526","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450526","url":null,"abstract":"Protocol transducer which realizes translations between multiple protocols is one of the key components in IP-based design methodology. Although there have been researches on automatic synthesis of such protocol transducers, they cannot efficiently deal with out-of-order type communications frequently found in the state-of-the-art protocols. In this paper we present an automatic synthesis method which can deal with complicated state-of-the-art protocols by clearly separating control and datapath parts of the synthesized protocol transducers and introducing four types of configurations in the datapath parts of the protocol transducers. We also present a formal verification method based on inclusion checking between the given protocol transducer to be verified and the all possible protocol transducers which can be generated through our synthesis method. By using simulation-based filtering methods followed by a complete analysis of the entire design and state space, large and complicated protocol transducers can be efficiently and formally verified. Experimental results show their practical usefulness even for protocol transducers for complicated state-of-the-art protocols.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115601317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3