2010 11th International Symposium on Quality Electronic Design (ISQED)最新文献_第10页

Photomasks and the enablement of circuit design complexity 光掩模和电路设计复杂性的实现

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450555

P. Buck, F. Kalk, C. West

引用次数: 0

BSIM4-based lateral diode model for LNA co-designed with ESD protection circuit 基于bsim4的LNA横向二极管模型与ESD保护电路协同设计

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450396

Ming-Ta Yang, Yang Du, C. Teng, Tony Chang, E. Worley, K. Liao, Y. Yau, G. Yeap

引用次数: 6

Constraint analysis and debugging for multi-million instance SoC designs 数百万实例SoC设计的约束分析与调试

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450540

Long Fei, L. Mize, Cho Moon, Bill Mullen, Sonia Singhal

引用次数: 1

Formal verification of Full-Wave Rectifier using SPICE circuit simulation traces 使用SPICE电路仿真轨迹的全波整流器的正式验证

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450556

K. Lata, H. S. Jamadagni

{"title":"Formal verification of Full-Wave Rectifier using SPICE circuit simulation traces","authors":"K. Lata, H. S. Jamadagni","doi":"10.1109/ISQED.2010.5450556","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450556","url":null,"abstract":"In this paper, we present a case study of formal verification of analog and mixed signal designs using SPICE circuit simulation traces. We consider verifying safety properties of Full Wave Rectifier (FWR) using SPICE circuit simulation traces. We follow the formal verification approach of [1] where authors have used the SPICE circuit simulation traces for doing the formal analysis of the Analog and Mixed Signal circuits. We have used the Checkmate tool from CMU [2], which is a public domain formal verification tool for hybrid systems. Checkmate is built on the top of the Simulink/Stateflow Framework (SSF) from MATLAB from Math Works. Due to restriction imposed by Checkmate it necessitates to make the changes in the Checkmate implementation to implement the complex and non-linear systems. FWR has been implemented by using Checkmate custom blocks and Simulink blocks from MATLAB. The FWR model has been implemented in LTSPICE. The formal verification has been done for both the implementation i.e. Simulink implementation as well as LTSPICE implementation. We are able to efficiently verify the safety properties of the full wave rectifier using simulation traces from Simulink model and LTSPICE simulation.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130275821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Linear time calculation of state-dependent power distribution network capacitance 状态相关配电网电容的线性时间计算

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450399

Shiho Hagiwara, K. Yamanaga, Ryo Takahashi, K. Masu, Takashi Sato

引用次数: 2

Clock routing for structured ASICs with via-configurable fabrics 具有可配置结构的结构化asic的时钟路由

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450489

Rung-Bin Lin, I.-W. Lee, Wen-Hao Chen

引用次数: 0

Multiplexed trace signal selection using non-trivial implication-based correlation 多路跟踪信号选择使用非平凡的隐含相关

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450503

S. Prabhakar, M. Hsiao

引用次数: 21

Yield-constrained digital circuit sizing via sequential geometric programming 基于顺序几何规划的产量约束数字电路尺寸

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450391

Y. Ben, L. Ghaoui, K. Poolla, C. Spanos

引用次数: 4

Slack-based approach for peak power reduction during transition fault testing 过渡故障测试中基于松弛的峰值功率降低方法

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450516

M. Baby, V. Sarathi

{"title":"Slack-based approach for peak power reduction during transition fault testing","authors":"M. Baby, V. Sarathi","doi":"10.1109/ISQED.2010.5450516","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450516","url":null,"abstract":"Peak power consumption during test for the low power devices is a major concern [2, 3, 4]. Excessive peak power may result in test failures of functionally good devices. Huge peaks in the instantaneous power consumption will result in high rates of change of current (di/dt) causing adverse noise effects like VDD-drop and ground-bounce [1, 2, 3, 4]. Also, a high frequency of occurrence of high di/dt may cause severe decrease in the reliability of the circuit [1]. Hence the process of testing low power devices must be peak power aware. This paper provides a method to minimize the peak power during speed capture phase by partitioning the nodes into two zones based on their timing slacks. One of the zones contains the timing-critical nodes, while the other contains the non timing-critical ones. Each zone may be split into multiple bins. Test patterns are generated independently for each bin, targeting the nodes belonging to that bin alone, thus reducing the size of the target set. It is very important that the peak power consumed by the test patterns for each bin in the timing-critical zone is well within the tolerable limit. The bins in the non timing-critical zone may be allowed to have peak power consumptions very close to the limit or even marginally higher because the large positive slacks on these nodes will make up for the extra delay through the cells caused by VDD-drop/ground-bounce. This approach allows the designer to have a better control over each pattern and also helps to minimize the effects of high peak power and high di/dt.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124387795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Comparative analysis and study of metastability on high-performance flip-flops 高性能触发器亚稳态的比较分析与研究

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450482

David Li, P. Chuang, M. Sachdev

引用次数: 29