{"title":"Is built-in logic redundancy ready for prime time?","authors":"Chris Allsup","doi":"10.1109/ISQED.2010.5450435","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450435","url":null,"abstract":"With each new process generation, it becomes ever more challenging to maintain high yields of integrated circuits. Progressively lower yields potentially undermine the profits of semiconductor companies across all industry segments. Embedding redundant logic into designs can improve product yields, but is this economically viable for most systems-on-chip? This paper attempts to answer this fundamental question. After describing an example architecture for built-in logic redundancy (BILR), we examine precisely how the BILR design and test parameters affect the area overhead, test execution time and yield of the redundant system. After conveying the cost model, we present analysis results showing that redundancy could be cost-effective, depending on a number of cost infrastructure variables that include the parameters of the BILR system itself.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"43 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120866846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Datta, M. Warhadpande, D. Heaton, S. Aarthi, R. Jonnavithula
{"title":"Case studies of mixed-signal DFT","authors":"R. Datta, M. Warhadpande, D. Heaton, S. Aarthi, R. Jonnavithula","doi":"10.1109/ISQED.2010.5450517","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450517","url":null,"abstract":"Significant growth in demand for mixed signal parts, and an increased level of integration of such parts into SOCs have created or exacerbated several test related challenges. Techniques like design-for-testability (DFT) have been applied to overcome some of these challenges. In this paper, we present case studies of one of the most common DFT techniques for mixed-signal devices, namely, analog loopback testing of data converters. Theoretical analysis of loopback testing is presented, along with silicon test results for stand-alone, internal loopback and external loopback testing of data converter in an industrial chip. These results are used to evaluate the feasibility and effectiveness of these two variants of mixed-signal DFT, i.e., internal and external loopback testing of data converters.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127290711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Mathew, H. Rahaman, A. Jabir, S. Mohanty, D. Pradhan
{"title":"On the design of different concurrent EDC schemes for S-Box and GF(p)","authors":"J. Mathew, H. Rahaman, A. Jabir, S. Mohanty, D. Pradhan","doi":"10.1109/ISQED.2010.5450467","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450467","url":null,"abstract":"Recent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure and reliable implementation of cryptographic algorithms in hardware must be able to detect or correct such malicious attacks. Error detection/correction (EDC), through fault tolerance, could be an effective way to mitigate such fault attacks in cryptographic hardware. To this end, we analyze the area, delay, and power overhead for designing the S-Box, which is one of the main complex blocks in the Advanced Encryption Standard (AES), with error detection and correction capability. We use multiple Parity Predictions (PPs), based on various error correcting codes, to detect and correct errors. Various coding techniques are presented, which include simple parity prediction, split parity codes, Hamming, Hsiao, and LDPC codes. The S-Box, GF(p), and PP circuits are synthesized from the specifications, while the decoding and correction circuits are combined to form the complete designs. The analysis shows a comparison of the different approaches characterized by their error detection capability.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130730149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Leakage temperature dependency modeling in system level analysis","authors":"Huang Huang, Gang Quan, Jeffrey Fan","doi":"10.1109/ISQED.2010.5450539","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450539","url":null,"abstract":"As the semiconductor technology continues its marching toward the deep sub-micron domain, the strong relation between leakage current and temperature becomes critical in power-aware and thermal-aware design for electronic systems. Previous circuit-level research results can capture the leakage/temperature dependency accurately, but can be too complex and thus ineffective in high level system design. In this paper, we study a large spectrum of leakage power models that are able to account for the leakage/temperature dependency, and in the meantime, are simple enough and suitable for system level design. We analyze and compare the tradeoff between the complexity and accuracy of these models empirically. Our experimental results strengthen the important role that the leakage power consumption plays in the electronic system design as the transistor size continues to shrink. More importantly, our results highlight the fact that it is vital to take the leakage/temperature and leakage/supply voltage dependency into considerations for high level power and thermal aware system level design.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133410279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Bickford, N. Habib, John Goss, R. McMahon, R. Joshi, R. Kanj
{"title":"Use of scalable Parametric Measurement Macro to improve semiconductor technology characterization and product test","authors":"J. Bickford, N. Habib, John Goss, R. McMahon, R. Joshi, R. Kanj","doi":"10.1109/ISQED.2010.5450445","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450445","url":null,"abstract":"Use of a Scaling Parametric Macro (SPM) provides more accurate product level environment parametric information than scribe line (Kerf) structures. This paper compares drive current (Ion) data obtained with the SPM macros to scribe line structure Ion measurements. SPM macros provide less variation than scribe line structures. Since SPM is small enough to be included in all products, the SPM macro provides improved Ion product screening","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133289265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reliability analysis of analog circuits by lifetime yield prediction using worst-case distance degradation rate","authors":"X. Pan, H. Graeb","doi":"10.1109/ISQED.2010.5450477","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450477","url":null,"abstract":"As semiconductor technology scales, manufacture process-related statistical variations and lifetime-dependent degradations contribute directly to the fluctuations of transistor parameters and circuit performances. Considering alone either the static process variation or the nominal lifetime degradation cannot ensure a robust design during the entire lifetime. It is thus highly necessary to obtain lifetime degradation information considering underlying process variation early at design phase. This paper establishes an innovative framework to predict the analog circuit behavior in its lifetime considering both process variations and degradation effects based on geometric lifetime yield analysis using worst-case distance degradation rate. Compared to Monte-Carlo-based methods and numerical optimization solutions, only performance and statistical parameter sensitivity analysis are required in the proposed framework.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114244924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chenyue Ma, Hao Wang, Xiufang Zhang, F. He, Yadong He, Xing Zhang, Xinnan Lin
{"title":"Asymmetric issues of FinFET device after hot carrier injection and impact on digital and analog circuits","authors":"Chenyue Ma, Hao Wang, Xiufang Zhang, F. He, Yadong He, Xing Zhang, Xinnan Lin","doi":"10.1109/ISQED.2010.5450542","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450542","url":null,"abstract":"This paper presents the asymmetric issue of FinFET device after hot carrier injection (HCI) effect and impact on the digital and analog circuits. The interface state distribution along the FinFET channel is first extracted from hot carrier injection experimental data, and then develops a compact FinFET model to simulate the impact on asymmetric distribution of interface states to the device characteristics. The results show that the asymmetric degradation is much more significant in Ids-Vds characteristics than in Ids-Vgs characteristics. On the other hand, digital and analogy circuits exhibit different asymmetric performance degradation in various operation cases.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133662413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hot carrier effects on CMOS phase-locked loop frequency synthesizers","authors":"Yang Liu, A. Srivastava","doi":"10.1109/ISQED.2010.5450392","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450392","url":null,"abstract":"Two CMOS phase-locked loop chips are designed and fabricated in 0.5 µm n-well CMOS process using single-ended voltage-controlled oscillator and differential voltage-controlled oscillator circuits. Hot carrier effects, jitter and phase noise performances are investigated and analyzed. On-chip measured experimental results show that for the phaselocked loop with the single-ended voltage-controlled oscillator working at 500 MHz carrier frequency, phase noise is −76 dBc/Hz at 10 kHz offset frequency and −119 dBc/Hz at 1 MHz offset frequency. For the phase-locked loop with differential voltage-controlled oscillator working at 500 MHz, phase noise reaches −82 dBc/Hz at 1 kHz offset frequency and −122 dBc/Hz at 1 MHz offset frequency. Tuning frequencies of the two phase-locked loops decrease about 100–200 MHz when subjected to four hours of hot carrier stress. The single-ended VCO gain decreases from 260 MHz to 70 MHz due to hot carrier stress. For the phase-locked loop with the differential voltage-controlled oscillator, a 50 ps RMS jitter increase is observed under hot carrier stress.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132807953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis of power supply induced jitter in actively de-skewed multi-core systems","authors":"Derek Chan, Matthew R. Guthaus","doi":"10.1109/ISQED.2010.5450490","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450490","url":null,"abstract":"This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and power supply variation in multi-core designs. Using the methodology, we compare four different de-skewing topologies (region-based, linear, ring, and a tree) for nominal performance and robustness to power supply variation. We conclude that under nominal conditions, the ring and line topologies are better with a large number of cores, but, when power supply is considered, the region topology is best.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133422942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Peng Du, Xiang Hu, Shih-Hung Weng, A. S. Arani, Xiaoming Chen, A. Engin, Chung-Kuan Cheng
{"title":"Worst-case noise prediction with non-zero current transition times for early power distribution system verification","authors":"Peng Du, Xiang Hu, Shih-Hung Weng, A. S. Arani, Xiaoming Chen, A. Engin, Chung-Kuan Cheng","doi":"10.1109/ISQED.2010.5450511","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450511","url":null,"abstract":"A novel method of predicting the worst-case noise of a power distribution system is proposed in this paper. This method takes into account the effect of the transition time of load currents, and thus allows a more realistic worst-case noise prediction. A dynamic programming algorithm is introduced on the time-domain impulse response of the power distribution system, and a modified Knuth-Yao Quadrangle Inequality Speedup is developed which reduces the time complexity of the algorithm to O(nmlog n), where n is the number of discretized current values and m is the number of zeros of the system impulse response. With the algorithm, the worst-case noise behavior of the power distribution system is investigated with respect to the transition time. Experimental results show that assuming a zero current transition time leads to an overly pessimistic worst-case noise prediction.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116542441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}