2010 11th International Symposium on Quality Electronic Design (ISQED)最新文献_第4页

Accurate multi-specification DPPM estimation using layered sampling based simulation 精确的多规格DPPM估计使用分层采样为基础的模拟

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450446

E. Yilmaz

{"title":"Accurate multi-specification DPPM estimation using layered sampling based simulation","authors":"E. Yilmaz","doi":"10.1109/ISQED.2010.5450446","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450446","url":null,"abstract":"Unreasonably long test time and test cost forces the utilization of test compaction methods in production line. Test compaction methods reduce the test cost at the expense of degrading the test quality. When test compaction is used, it is essential to estimate the resulting test quality. Traditional Monte-Carlo simulation devotes most of the effort sampling the median region of the process parameters. However, defective escapes are generally marginal and accurate estimation of defective parts per million (DPPM) requires extensive simulation, especially when DPPM level is low. In this work, we aim at reducing the number of simulations required to estimate DPPM accurately through a two-step methodology exploiting the layered structure of process variation. In the first step, we generate an essential experiment set using a modified version of Taguchi's design of experiment method. We optimize this experiment set for accuracy in order to get a minimal set of experiments. In the second step, we emulate the low level process variation on the optimized essential experiment set. Instead of using traditional Monte-Carlo sampling method, employing layered sampling of process parameters enable us to achieve an accurate DPPMvalue for a substantially reduced number of simulations.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116200622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation 非对称6T SRAM，具有两相写入和分割位线差分传感，用于低压操作

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450400

Satyanand Nalam, V. Chandra, C. Pietrzyk, R. Aitken, B. Calhoun

引用次数: 21

Early-stage determination of current-density criticality in interconnects 互连中电流密度临界的早期测定

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450505

Göran Jerke, J. Lienig

{"title":"Early-stage determination of current-density criticality in interconnects","authors":"Göran Jerke, J. Lienig","doi":"10.1109/ISQED.2010.5450505","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450505","url":null,"abstract":"Excessive current density within interconnects is a major concern for IC designers, which if not effectively mitigated leads to electromigration and electrical overstress. This is increasingly a problem in modern ICs due to smaller feature sizes and higher currents associated with lower supply voltages. Detailed analysis of all interconnect nets is both time-consuming and cannot be done until physical design is complete, when it is too late for easy fixes. To address these problems, we introduce (i) a powerful terminal current model and (ii) an efficient methodology to determine the worst-case bounds on segment currents of the interconnect. This early-stage calculation enables nets to be separated into critical and non-critical sets; only the set of critical nets, which is typically considerably smaller, requires subsequent special consideration during physical design and layout verification due to current density design limits. The presented algorithms are fast enough to run on every net, and work with known and unknown net topology, leading to several practical uses, such as (i) the pre-layout identification of nets that are potentially troublesome and may need sizing, (ii) as filter to avoid time-consuming detailed current-density analysis of net layouts, and (iii) to evaluate the effect of interconnect temperature and process changes on the number and distribution of current-density-critical nets.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122080371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Antenna Violation Avoidance/Fixing for X-clock routing x时钟路由的天线冲突避免/修复

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450525

Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee

引用次数: 3

A novel low voltage current compensated high performance current mirror/NIC 一种新型的低电压电流补偿型高性能电流镜/NIC

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450537

K. Monfaredi, H. F. Baghtash, S. J. Azhari

引用次数: 15

Thermal-aware job allocation and scheduling for three dimensional chip multiprocessor 三维芯片多处理器的热感知作业分配与调度

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450547

Shaobo Liu, Jingyi Zhang, Qing Wu, Qinru Qiu

{"title":"Thermal-aware job allocation and scheduling for three dimensional chip multiprocessor","authors":"Shaobo Liu, Jingyi Zhang, Qing Wu, Qinru Qiu","doi":"10.1109/ISQED.2010.5450547","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450547","url":null,"abstract":"In this paper, we propose a thermal-aware job allocation and scheduling algorithm for three-dimensional (3D) chip multiprocessor (CMP). The proposed algorithm assigns hot jobs to the cores close to the heat sink and cool jobs to the cores far from the heat sink, subject to thermal constraints. The direct effect of the proposed algorithm on a 3D-CMP system is that, the heat from hot jobs is removed off the chip faster than the temperature-aware methods. Therefore we are able to keep the chip cooler and in better thermal condition. Experimental results show that, comparing to the temperature-aware method, our algorithm achieves: 1) less hot spots; 2) better performance; 3) smaller temporal temperature variation; 4) lower peak temperature. The proposed algorithm reduces hot spots by more than 95% when workload contains cool jobs; and by 36% when workload does not contain cool jobs. It also boosts the system performance by 5% on average under various workloads. The temporal temperature variation is reduced by 60% and its standard deviation is decreased by 50%. In addition, the proposed algorithm achieves 1.8°C ∼5°C reduction in peak temperature.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123813871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 42

A framework for logic-aware layout analysis 用于逻辑感知布局分析的框架

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450415

Patrick Gibson, Ziyang Lu, F. Pikus, Sridhar Srinivasan

引用次数: 15

Variation-aware speed binning of multi-core processors 多核处理器的变化感知速度分组

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450442

J. Sartori, A. Pant, Rakesh Kumar, Puneet Gupta

引用次数: 37

Is built-in logic redundancy ready for prime time? 内置的逻辑冗余准备好了吗?

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450435

Chris Allsup

引用次数: 5

Adaptive HCI-aware power gating structure 自适应hci感知功率门控结构

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450418

Kyung Ki Kim, Haiqing Nan, K. Choi

引用次数: 4