Efficient hierarchical discretization of off-chip power delivery network geometries for 2.5D electrical analysis

Power delivery network (PDN) design is becoming even more critical with the advent of progressively complex environments on and beyond the die. Multicore chips, mixed-signal designs with multiple reference voltages, and complex 3D packaging situations lead to complicated PDN geometries with high-frequency demands and sharpening edge rates even when on-core frequencies are relatively constant. Early design iterations of such PDNs remain infeasible with 3D full-wave simulators even with the latest breakthroughs in solver technology. For reasonably well designed structures and moderate frequencies, fast 2.5D tools (particularly in the most evolved form of multilayered finite difference method (MFDM) [1]) work well. However, application of these methods to complex layouts containing cutouts, slots, vias, microvias and non-Cartesian shapes is challenging. First, generating a layer-wise consistent mesh from the complex layout is nontrivial. Second, use of globally uniform meshing, as generally employed forces a choice between an inaccurate or inefficient solution. This paper proposes an algorithm for rapidly generating layerwise consistent adaptive rectangular meshes for multilayered PDNs with the aim of significantly enhancing the speed, capacity and versatility of 2.5D methods. An efficient implementation of MFDM based on the adaptive mesh has been made. Results show that the algorithm is general enough to extend the applicability of these methods from simple PDNs to complex real-world models.