2010 11th International Symposium on Quality Electronic Design (ISQED)最新文献_第3页

Scalable methods for the analysis and optimization of gate oxide breakdown 栅极氧化物击穿分析和优化的可扩展方法

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450507

Jian-wei Fang, S. Sapatnekar

引用次数: 17

Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration 考虑电路/实例/晶体管级应力概率的NBTI延迟退化估计的比较研究

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450508

Hiroaki Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye

引用次数: 22

Adaptive task allocation for multiprocessor SoCs 多处理器soc的自适应任务分配

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450524

Tongquan Wei, Yonghe Guo, Xiaodao Chen, Shiyan Hu

引用次数: 13

Coprocessor design space exploration using high level synthesis 利用高级综合技术进行空间协处理器设计探索

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450474

Avinash Lakshminarayana, Sumit Ahuja, S. Shukla

引用次数: 5

OBT implementation on an OTA-C band-pass filter OTA-C带通滤波器的OBT实现

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450427

P. Petrashin, G. Peretti, E. Romero

引用次数: 8

A convex optimization framework for leakage aware thermal provisioning in 3D multicore architectures 三维多核架构中泄漏感知热供给的凸优化框架

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450487

Sanghamitra Roy, Koushik Chakraborty

引用次数: 2

Design of low-power variation tolerant signal processing systems with adaptive finite word-length configuration 自适应有限字长结构的低功耗容差信号处理系统设计

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450551

Yang Liu, Jibang Liu, Tong Zhang

{"title":"Design of low-power variation tolerant signal processing systems with adaptive finite word-length configuration","authors":"Yang Liu, Jibang Liu, Tong Zhang","doi":"10.1109/ISQED.2010.5450551","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450551","url":null,"abstract":"This paper concerns the design of low power digital signal processing integrated circuits in the presence of significant process variations. The basic idea is to leave smaller-than-worst-case timing margin for improving energy efficiency during the design phase and selectively reduce the finite word-length of circuit datapaths in post-silicon to eliminate all the timing faults during the run time. This simple idea can be intuitively justified by the fact that process variations may render only a few post-silicon datapaths to timing faults, while reducing the finite word-length of a few datapaths in signal processing systems may not necessarily make the overall algorithm-level performance unacceptable in run time. We present a design flow to implement this method and propose a dual finite word-length configuration strategy to simplify its real-life realization. Using linear low-pass filter and Turbo code decoder design at 45nm node as case studies, we quantitatively demonstrate that this adaptive finite word-length configuration design strategy may effectively relax the timing margin and accordingly reduce the power consumption by over 18% over conventional worst-case design approach.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131251132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Adaptive power gating for function units in a microprocessor 微处理器中功能单元的自适应功率门控

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450407

K. Usami, T. Hashida, S. Koyama, Tatsuya Yamamoto, D. Ikebuchi, H. Amano, M. Namiki, Masaaki Kondo, Hiroshi Nakamura

{"title":"Adaptive power gating for function units in a microprocessor","authors":"K. Usami, T. Hashida, S. Koyama, Tatsuya Yamamoto, D. Ikebuchi, H. Amano, M. Namiki, Masaaki Kondo, Hiroshi Nakamura","doi":"10.1109/ISQED.2010.5450407","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450407","url":null,"abstract":"This paper describes adaptive fine-grain control to power gate function units based on temperature dependent break-even time (BET). An analytical model to express the temperature dependent BET is introduced and the accuracy of the model was examined. Results demonstrated that the model well represents the exponential decrease in BET with the temperature. Meanwhile, it was found that the accuracy gets worse at higher temperature and the cause is energy dissipation due to transient glitch at the wakeup. We propose four power-gating policies employing time-based or history-based approaches. Effectiveness in energy savings was evaluated using real design data of four function units in a microprocessor implemented in a 65nm technology. Results showed that introducing adaptive control to make use of temperature-dependent BET enhances energy savings by up to 21% in the time-based approach and by up to 18% in the history-based approach. The adaptive history-based policy with a limiter outperforms the adaptive time-based policy in energy savings and reduces the total energy of four function units to 11.8% at 100°C as compared to the non-power-gating case.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133373393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Efficient hierarchical discretization of off-chip power delivery network geometries for 2.5D electrical analysis 用于2.5D电分析的片外供电网络几何图形的有效分层离散化

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450518

M. Mondal, J. Pingenot, V. Jandhyala

{"title":"Efficient hierarchical discretization of off-chip power delivery network geometries for 2.5D electrical analysis","authors":"M. Mondal, J. Pingenot, V. Jandhyala","doi":"10.1109/ISQED.2010.5450518","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450518","url":null,"abstract":"Power delivery network (PDN) design is becoming even more critical with the advent of progressively complex environments on and beyond the die. Multicore chips, mixed-signal designs with multiple reference voltages, and complex 3D packaging situations lead to complicated PDN geometries with high-frequency demands and sharpening edge rates even when on-core frequencies are relatively constant. Early design iterations of such PDNs remain infeasible with 3D full-wave simulators even with the latest breakthroughs in solver technology. For reasonably well designed structures and moderate frequencies, fast 2.5D tools (particularly in the most evolved form of multilayered finite difference method (MFDM) [1]) work well. However, application of these methods to complex layouts containing cutouts, slots, vias, microvias and non-Cartesian shapes is challenging. First, generating a layer-wise consistent mesh from the complex layout is nontrivial. Second, use of globally uniform meshing, as generally employed forces a choice between an inaccurate or inefficient solution. This paper proposes an algorithm for rapidly generating layerwise consistent adaptive rectangular meshes for multilayered PDNs with the aim of significantly enhancing the speed, capacity and versatility of 2.5D methods. An efficient implementation of MFDM based on the adaptive mesh has been made. Results show that the algorithm is general enough to extend the applicability of these methods from simple PDNs to complex real-world models.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115072351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Soft error rate determination for nanoscale sequential logic 纳米级顺序逻辑的软错误率测定

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI: 10.1109/ISQED.2010.5450421

Fan Wang, V. Agrawal

引用次数: 26